82371AB Datasheet, PDF (199/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
Synchronous DMA Timings
The timings for Ultra DMA/33 are programmed into the Ultra DMA/33 Timing Register. The programmable
timings include Cycle Time (CT) and Ready to Pause (RP) time. The Cycle Time represents the minimum pulse
width of active data strobe (STROBE) signal. The Ready to Pause time represents the number of PCI clocks
PIIX4 waits from negation of DMARDY# to the assertion of STOP when it desires to stop a burst read
transaction.
10.0. USB HOST CONTROLLER FUNCTIONAL DESCRIPTION
PIIX4 contains a USB Host Controller (HC). The Host Controller includes the root hub with two USB ports. This
permits connection of two USB peripheral devices directly to PIIX4 without an external hub. If more devices are
required, an external hub can be connected to either of the built-in ports. The USB’s PCI configuration registers
are located in function 2, PCI configuration space. The PIIX4 Host Controller completely supports the standard
Universal Host Controller Interface (UHCI) and thus, takes advantage of the standard software drivers written to
be compatible with UHCI. Figure 9 shows a conceptual view of a USB system. UHCI consists of two parts—
Host Controller Driver (HCD) and Host Controller (HC). The Host Controller interfaces to the USB system
software in the host via the HCD. The HCD software manages the Host Controller operation and is responsible
for scheduling the traffic on USB by posting and maintaining transactions in system memory. HCD is part of the
system software and is typically provided by the operating system vendor. HCD provides the software layer
between the PIIX4’s Host Controller and the USBD software layer (also located in the operating system). The
UHCI’s HCD software interprets requests from the USBD and builds Frame List, Transfer Descriptor, Queue
Head, and data buffer data structures for the Host Controller. The data structures are built in system memory
and contain all necessary information to provide end-to-end communication between client software in the host
and devices on the USB.
The PIIX4’s Host Controller moves data between system memory and devices on the USB by processing these
data structures and generating the transaction on USB. The Host Controller executes the schedule lists
generated by HCD and reports the status of transactions on the USB to HCD. Command execution includes
generating serial bus token and data packets based on the command and initiating transmission on USB. For
commands that require the Host Controller to receive data from the USB device, the Host Controller receives the
data and then transfers it to the system memory pointed to by the command. The UHCI’s HCD provides
sufficient commands and data to keep ahead of the Host Controller execution and analyzes the results as the
commands are completed.
For additional information on the functionality of PIIX4 USB Host Controller, refer to the Universal Host Controller
Interface (UHCI) Design Guide, Revision 1.1 available from Intel Literature Center with order number 297650-
002. Note that the UHCI Design Guide refers to USB ports 1 and 2. The PIIX4 USB ports are ports 0 and 1
respectively.
Additions to the PIIX4 USB interface beyond UHCI, revision 1.1 include support for over-current detection on
USB ports 0 and 1. If an over-current condition is detected on a USB port, that port will be disabled. Bits 10:11 in
each Port Status and Control register are used to report over-current conditions.
PRELIMINARY
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4/9/97 2:23 PM PIIX4aDS
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