82371AB Datasheet, PDF (101/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
Bit 2
0
Table 15. Interrupt/Activity Status Combinations
Bit 0
Description
0 Error condition. If the IDE DMA Error bit is 1, there is a problem transferring data to/from
memory. Specifics of the error have to be determined using bus-specific information.
If the Error bit is 0, the PRD specified a smaller buffer size than the programmed IDE transfer
size.
5.2.3. BMIDTPX—BUS MASTER IDE DESCRIPTOR TABLE POINTER REGISTER (IO)
Address Offset:
Default Value:
Attribute:
Primary Channel—Base + 04h; Secondary Channel—Base + 0Ch
00000000h
Read/Write
This register provides the base memory address of the Descriptor Table. The Descriptor Table must be DWord
aligned and not cross a 4-Kbyte boundary in memory.
Bit
Description
31:2 Descriptor Table Base Address (DTBA). Bits [31:2] correspond to A[31:2].
1:0 Reserved.
PRELIMINARY
101
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