82371AB Datasheet, PDF (239/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

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82371AB (PIIX4)
Table 41. Core Well Power and PWROK Activated Signals Timings
Sym
Parameter
Min Max Unit Notes
t20 Core Well Power and PWROK Inactive to CPU_STP# and PCI_STP#
Float
1 RTC 1
t21 Core Well Power and PWROK Inactive to PCIRST# Active
1 RTC 1
t22 Core Well Power and PWROK Inactive to CPURST Active
1 RTC 1
t23 Core Well Power and PWROK Inactive to SLP# Active
1 RTC 1
t24 Core Well Power and PWROK Inactive to STPCLK# Active
1 RTC 1
t25 CPU_STP# and PCI_STP# Float to Clocks Running
2
t26 PWROK Active to CPU_STP# and PCI_STP# Active
1 RTC 1
t27 CPU_STP# and PCI_STP# Active to Clocks Stopped
2
NOTES:
1. These signals are controlled off an internal RTC clock. 1 RTC unit is approximately 32 µs.
2. There are no specific requirements for these timings related to PIIX4. The system manufacturer should
make sure that the clocks on power up meet any other system specifications. As a minimum, the clocks
must be available and stable after time t30 shown in Figure 22.
PRELIMINARY
239
4/9/97 2:23 PM PIIX4aDS
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(until publication date)