82371AB Datasheet, PDF (95/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
5.1.11. SIDETIM—SLAVE IDE TIMING REGISTER (FUNCTION 1)
Address Offset:
Default Value:
Attribute:
44h
00h
Read/Write Only
This register controls PIIX4’s IDE interface and selects the timing characteristics for the slave drives on each
IDE channel. This allows for programming of independent operating modes for each IDE agent. This register has
no affect unless the SITRE bit is enabled in the IDETIM Register. See Table 14 for programming values for
various PIO Timing Modes.
Bit
Description
7:6 Secondary Drive 1 IORDY Sample Point (SISP1). This field selects the number of PCI clocks
between SDIOx# assertion and the first SIORDY sample point for the slave drive on the secondary
channel.
Bits[7:6]
00
01
10
11
Number Of Clocks
5
4
3
2
5:4 Secondary Drive 1 Recovery Time (SRTC1). This field selects the minimum number of PCI clocks
between the last SIORDY# sample point and the SDIOx# strobe of the next cycle for the slave drive
on the secondary channel.
Bits[5:4]
Number Of Clocks
00
4
01
3
10
2
11
1
3:2 Primary Drive 1 IORDY Sample Point (PISP1). This field selects the number of PCI clocks
between PDIOx# assertion and the first PIORDY sample point for the slave drive on the primary
channel.
Bits[3:2]
Number Of Clocks
00
5
01
4
10
3
11
2
1:0 Primary Drive 1 Recovery Time (PRTC1). This field selects the minimum number of PCI clocks
between the last PIORDY# sample point and the PDIOx# strobe of the next cycle for the slave drive
on the primary channel.
Bits[1:0]
Number Of Clocks
00
4
01
3
10
2
11
1
PRELIMINARY
95
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)