82371AB Datasheet, PDF (263/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
11.5.2. SMI# GENERATION EVENTS
Some of the events can also generate the ACPI compatible System Control Interrupt (SCI) or suspend state
resume events. The SMI# or SCI is selectable with the [SCI_EN] bit. When set to 1, these events generate an
SCI, if enabled. When reset, these events generate an SMI#, if enabled. See the “APIC Support” section for
additional details on ACPI and SCI. See the “Suspend/Resume and Power Plane Control” section for additional
details on system suspend and resume.
When an event generates an SMI# event, it sets a status bit. Status bits from various sources are combined
together (“ORed”) to create hierarchical status bits. The hierarchical status bits cannot be reset by software.
Their respective “children” status bits must all be cleared in order for them to clear.
PWRBTN# Asserted:
[PWRBTN_EN]
[PWRBTNOR_EN]
[PWRBTN_STS]
[PWRBTNOR_STS]
— The PWRBTN# input signal can be used to generate an SMI# upon its assertion. It contains
a 16-ms debounce circuit to filter out mechanical switch bounce. When asserted, it will set
the [PWRBTN_STS] bit after the 16-ms debounce. This will cause generation of an SMI# if
enabled. If the PWRBTN# signal is held active for greater than 4 seconds and Power Button
Override feature is enabled, the [PWRBTN_STS] bit is cleared, the [PWRBTNOR_STS] bit
is set, and PIIX4 will automatically transition the system into the Soft Off Suspend State (see
the “Suspend/Resume and Power Plane Control” section for more details on Soft Off
Suspend). This signal can also be used to generate an SCI or a suspend state resume
event.
LID Asserted:
[LID_EN]
[LID_STS]
— Polarity Select:
[LID_POL]
— The LID signal, when asserted, sets the [LID_STS] bit after a 16-ms debounce, and when
enabled, generates an SMI#. The assertion polarity can be controlled to allow system code
to detect when LID signal transitions from low to high or high to low. This signal can also be
used to generate an SCI or a suspend state resume event.
GPI1 Asserted:
[GPI_EN]
[GPI_STS]
— The GPI1 signal, when asserted LOW, will set the [GPI_STS] bit, and when enabled will
generate an SMI#. This signal can also be used to generate an SCI or a suspend state
resume event.
EXTSMI# Asserted:
[EXTSMI_EN]
[EXTSMI_STS]
— The EXTSMI# signal, when asserted, will set the [EXTSMI_STS] bit, and when enabled will
generate an SMI#. This signal can also be used to generate a suspend state resume event.
SMBus Events:
[ALERT_EN]
[SLV_EN]
[SHDW1_EN]
[SHDW2_EN]
[ALERT_STS]
[SLV_STS]
[SHDW1_STS]
[SHDW2_STS]
— The System Management Bus (SMBus) controller has various means to generate an SMI#.
These can also be used to generate a suspend state resume events. See the “SMBus
Functional Description” section on page 265 for additional information.
PRELIMINARY
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