82371AB Datasheet, PDF (57/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
Bit
Description
7 DMA Reserved Page Register Aliasing Control (DMAAC). When DMAAC=0, PIIX4 aliases PCI
I/O accesses in the 90–9Fh range to the 80–8Fh range. In this case, PIIX4 only forwards PCI write
accesses to 90–9Fh to the ISA Bus. ISA Master accesses to 90−9Fh range are forwarded
to PCI.
When DMAAC=1, PIIX4 disables aliasing for the entire 90–9Fh range (they are considered ISA bus
register locations). PIIX4 forwards read and write accesses to these registers to ISA. ISA Master
accesses to 90−9Fh range are ignored by PIIX4.
Note, that port 92h is always a distinct register in the 90–9Fh range and is never forwarded from the
PCI bus to the ISA Bus. It is also never forwarded from ISA to PCI or from ISA to the internal Port 92
register.
PIIX4 does not support aliasing of the 90h range for the Distributed DMA function, even if aliasing is
enabled.
6 8-Bit I/O Recovery Enable. 1=Enable the recovery time programmed in bits [5:3]. 0=Disable
recovery times in bits [5:3] and use the recovery timing of 3.5 SYSCLKs.
5:3 8-Bit I/O Recovery times. When bit 6=1, this 3-bit field defines the additional number of SYSCLKs
added to standard 3.5 SYSCLK recovery time for 8-bit I/O.
Bit[5:3]
001
010
011
100
SYSCLK
1
2
3
4
Bit[5:3]
101
110
111
000
SYSCLK
5
6
7
8
2 16-Bit I/O Recovery Enable. 1=Enable the recovery times programmed in bits [1:0]. 0=Disable
programmable recovery times in bits [1:0] and use the recovery timing of 3.5 SYSCLKs.
1:0 16-Bit I/O Recovery Times. When bit 2=1, this 2-bit defines the additional number of SYSCLKs
added to standard 3.5 SYSCLK recovery time for 16-bit I/O.
Bit[1:0]
00
01
10
11
SYSCLK
3
1
2
4
4.1.9. XBCS—X-BUS CHIP SELECT REGISTER (FUNCTION 0)
Address Offset:
Default Value:
Attribute:
4E−4Fh
03h
Read/Write
This register enables or disables accesses to an external RTC, keyboard controller, I/O APIC, a secondary
controller, and BIOS. Disabling any of these bits prevents the device’s chip select and X-Bus output enable
control signal (XOE#) from being generated. This register also provides coprocessor error and mouse functions.
Bit
15:11 Reserved.
Description
PRELIMINARY
57
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)