82371AB Datasheet, PDF (139/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
Bit
Description
9:3 Reserved.
2 Global Release (GBL_RLS)—R/W. 1=A 1 written to this bit position will cause an SMI# to be
generated and BIOS_STS bit set if enabled by the BIOS_EN bit. 0=No SMI# generated. This bit is
used by the ACPI software to raise an event to the BIOS software.
1 Bus Master Reload Enable (BRLD_EN_BM)—R/W. 1=Enable the generation of a Burst or Stop
Break event upon setting of the BM_STS bit. 0=Disable.
0 SCI Enable (SCI_EN)—R/W. 1=Enable generation of SCI upon assertion of PWRBTN_STS,
LID_STS, THRM_STS, or GPI_STS bits. 0=Disable.
7.2.4. PMTMR—POWER MANAGEMENT TIMER REGISTER (IO)
I/O Address:
Default Value:
Attribute:
Base + (08h)
00h
Read Only
Bit
Description
23:0 Timer Value (TMR_VAL)—RO. This field returns the running count of the power management timer.
This is a 24-bit counter that runs off a 3.579545-MHz clock. The timer is reset to an initial value of 0
during a PCI reset, and then continues counting unless the 14.31818-MHz OSC input to the chip is
stopped. If the clock is restarted without a PCI reset, then the counter will continue counting from
where it stopped. When bit 23 of the timer transitions from high-to-low or low-to-high, the
TMROF_STS bit is set. If the TMROF_EN bit is set an SCI interrupt is also generated.
7.2.5. GPSTS—GENERAL PURPOSE STATUS REGISTER (IO)
I/O Address:
Default Value:
Attribute:
Base + (0Ch)
00h
Read/Write
Bit
Description
15:12 Reserved.
11 LID Status (LID_STS)—R/WC. 1=LID signal has been asserted. 0=LID signal has not been
asserted. Assertion level is dependent upon polarity enable bit LID_POL value. If the LID_EN bit is
set then the setting of the LID_STS bit will generate an SCI, SMI# or resume event. This bit is only
set by hardware and can only be reset by writing a 1 to this bit position.
10 Ring Status (RI_STS)—R/WC. 1=Ring Indicate RI# signal has been asserted. 0=RI# has not been
asserted. If the RI_EN bit is set, the setting of the RI_STS bit generates a resume event. This bit is
only set by hardware and can only be reset by writing a 1 to this bit position.
9 GPI Status (GPI_STS)—R/WC. 1=GPI1# signal has been asserted. 0=GPI1# has not been
asserted. If the GPI_EN bit is set then the setting of the GPI_STS bit will generate an SCI, SMI# or
resume event. This bit is only set by hardware and can only be reset by writing a 1 to this bit
position.
PRELIMINARY
139
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)