82371AB Datasheet, PDF (71/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
4.2.1.5.
RWAMB—Read/Write All Mask Bits (IO)
I/O Address:
Default Value:
Attribute:
Channels 0–3—0Fh; Channels 4–7—0DEh
Bit[3:0]=1; Bit[7:4]=0 (CPURST or Master Clear)
Read/Write
A channel’s mask bit is automatically set to 1 when the Current Byte/Word Count Register reaches terminal
count (unless the channel is programmed for autoinitialization). Setting bits [3:0] to 1 disables all DMA requests
until a clear mask register instruction enables the requests. Note that, masking DMA channel 4 (DMA controller
2, channel 0), masks DMA channels [3:0]. Also Note that, Masking DMA controller 2 with
a write to port 0DEh also masks DREQ assertions from DMA controller 1.
Bit
Description
7:4 Reserved. Must be 0.
3:0 Channel Mask Bits. 1=Disable the corresponding DREQ(s); 0=Enable the corresponding DREQ(s).
Bit
Channel
0
0 (4)
1
1 (5)
2
2 (6)
3
3 (7)
4.2.1.6.
DS—DMA Status Register (IO)
I/O Address:
Default Value:
Attribute:
Channels 0–3—08h; Channels 4–7—0D0h
00h
Read Only
Each DMA controller has a read-only DMA Status Register that indicates which channels have reached terminal
count and which channels have a pending DMA request.
Bit
Description
7:4 Channel Request Status. When a valid DMA request is pending for a channel (on its DREQ signal
line), the corresponding bit is set to 1. When a DMA request is not pending for a particular channel,
the corresponding bit is set to 0. The source of the DREQ may be hardware or a software request.
Note that channel 4 does not have DREQ or DACK lines, so the response for
a read of DMA2 status for channel 4 is irrelevant.
Bit
Channel
4
0
5
1 (5)
6
2 (6)
7
3 (7)
3:0 Channel Terminal Count Status. 1=TC is reached; 0=TC is not reached.
Bit
Channel
0
0
1
1 (5)
2
2 (6)
3
3 (7)
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