82371AB Datasheet, PDF (255/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
Table 49. On to STD/SOff Timings
Sym
Parameter
Min Max Unit Notes
t103 CPU_STP# and PCI_STP# Inactive to STPCLK# Active
1
RTC 1, 2
t104 STPCLK# Active to SLP# Active
1
RTC 1, 3
t105 SLP# Active to SUS_STAT[1:2]# Active
1
RTC
1
t106 SUS_STAT[1:2]# Active to CPU_STP# and PCI_STP# Active
1
RTC
1
t107 CPU_STP# and PCI_STP# Inactive to Clocks Stopped
2 PCICLK 1, 4, 5
t108 CPU_STP# and PCI_STP# Inactive to SUS[A:C]# Active
1
RTC
1
t109 SUS[A:C]# Active to SUSCLK Low
1
RTC
1
t110 SUS[A:C]# Active to PWROK Inactive
0
ns
6
t111 PWROK Inactive to CPU_STP# and PCI_STP# Float
1
RTC
1
t112 PWROK Inactive to PCI_RST# Active
1
RTC
1
t113 PWROK Inactive to CPURST Active
1
RTC
1
t114 PWROK Inactive to SLP# Inactive
1
RTC
1
t115 PWROK Inactive to STPCLK# Inactive
1
RTC
1
t116 CPU_STP# and PCI_STP# Float to Clocks Invalid
0
ns
1
t117 PWROK Inactive to Core Well Power Removed
0
ns
t118 Core Well Power Removed to PCI_STP# and CPU_STP# Invalid 0
ns
t119 Core Well Power Removed to PCIRST# Invalid
0
ns
t120 Core Well Power Removed to CPURST Invalid
0
ns
t121 Core Well Power Removed to SLP# Invalid
0
ns
t122 Core Well Power Removed to STPCLK# Invalid
0
ns
NOTES:
1. These signals are controlled off the internal RTC clock. 1 RTC is approximately 32 µs.
2. CPU_STP# and PCI_STP# will only be active if system is under clock control.
3. This transition will also wait for the Stop Grant cycle to execute.
4. It is up to the system vendor to determine if CPU_STP# and PCI_STP# signals are used to control system
clocks.
5. See Figure 18 and Figure 19 for exact PCICLK requirements for use with PC/PCI DMA and Serial IRQs.
6. It is up to the system vendor to determine if SUS[A:C]# signals are used to control system power planes. If
power remains applied to system board and PWROK stays active during STD, the PIIX4 signals remain in
the states shown after t110.
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4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
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