82371AB Datasheet, PDF (35/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
Name
SUSB#/
GPO15
SUSC#/
GPO16
SUS_STAT1#/
GPO20
SUS_STAT2#/
GPO21
THRM#/
GPI8
ZZ/
GPO19
Type
Description
O SUSPEND PLANE B CONTROL. Control signal asserted during power
management suspend states. SUSB# is primarily used to control the secondary
power plane. This signal is asserted during STR and STD suspend states. If the
power plane control is not needed, this pin can be used as a general-purpose output.
During Reset: Low
After Reset: High
During POS: High/GPO
O SUSPEND PLANE C CONTROL. Control signal asserted during power
management suspend states, primarily used to control the tertiary power plane.
It is asserted only during STD suspend state. If the power plane control is not
needed, this pin can be used as a general-purpose output.
During Reset: Low
After Reset: High
During POS: High/GPO
O SUSPEND STATUS 1. This signal is typically connected to the Host-to-PCI bridge
and is used to provide information on host clock status. SUS_STAST1# is asserted
when the system may stop the host clock, such as Stop Clock or during POS, STR,
and STD suspend states. If this function is not needed, this pin can be used as a
general-purpose output.
During Reset: Low
After Reset: High
During POS: Low/GPO
O SUSPEND STATUS 2. This signal will typically connect to other system peripherals
and is used to provide information on system suspend state. It is asserted during
POS, STR, and STD suspend states. If this function is not needed, this pin can be
used as a general-purpose output.
During Reset: Low
After Reset: High
During POS: Low/GPO
I THERMAL DETECT. Active low signal generated by external hardware to start the
Hardware Clock Throttling mode. If enabled, the external hardware can force the
system to enter into Hardware Clock Throttle mode by asserting THRM#. This
causes PIIX4 to cycle STPCLK# at a preset programmable rate. If this function is not
needed, this pin can be used as a general-purpose input.
O LOW-POWER MODE FOR L2 CACHE SRAM. This signal is used to power down a
cache’s data SRAMs when the clock logic places the CPU into the Stop Clock.
If this function is not needed, this pin can be used as a general-purpose output.
During Reset: Low
After Reset: Low
During POS: Low
2.1.11. GENERAL PURPOSE INPUT AND OUTPUT SIGNALS
Some of the General Purpose Input and Output signals are multiplexed with other PIIX4 signals. The usage is
determined by the system configuration.
The default pin usage is shown in Table 1 and Table 2. The configuration can be selected via the General
Configuration register and X-Bus Chip Select register.
Name
GPI[21:0]
Type
Description
I GENERAL PURPOSE INPUTS. These input signals can be monitored via the GPIREG
register located in Function 3 (Power Management) System IO Space at address
PMBase+30h. See Table 1 for details.
PRELIMINARY
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4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)