82371AB Datasheet, PDF (241/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
Table 42. Mechanical Off to On Timings
Sym
Parameter
Min Max Unit Notes
t28 SUS[A:C]# Inactive to CPU_STP# and PCI_STP# Inactive
16
ms
1
t29 CPU_STP# and PCI_STP# Inactive to Clocks Running
2 PCICLK 2
t30 CPU_STP# and PCI_STP# Inactive to SUS_STAT[1:2]# Inactive
1
ms
t31 SUS_STAT[1:2]# Inactive to SUSCLK Running
1
RTC
3
t32 SUS_STAT[1:2]# Inactive to PCI_RST# Inactive
1
RTC
3
t33 PCI_RST# Inactive to CPURST Inactive
1
RTC
3
NOTES:
1. This transition requires both a minimum of 16-ms wait for clock synthesizer PLL lock and PWROK to be
active. If PWROK goes active after 16 ms from SUS[A:C]# inactive, the transition will occur a minimum of 1
RTC period from PWROK active.
2. See Figure 18 and Figure 19 for exact PCICLK requirements for use with PC/PCI DMA and Serial IRQs.
3. These signals are controlled off an internal RTC clock. 1 RTC unit is approximately 32 µs.
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