82371AB Datasheet, PDF (147/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
Bit
Description
10 Device 5 Idle Enable (IDL_EN_DEV5)—R/W. 1=Enable the device monitor 5 idle reload events to
reload the device monitor 5 idle timer. 0=Disable.
9 Device 4 Trap Enable (TRP_EN_DEV4)—R/W. 1=Enable generation of a trap SMI for accesses to
the device monitor 4 enabled trap decode ranges. 0=Disable.
8 Device 4 Idle Enable (IDL_EN DEV4)—R/W. 1=Enable the device monitor 4 idle reload events to
reload the device monitor 4 idle timer. 0=Disable.
7 Device 3 Trap Enable (TRP_EN_DEV3)—R/W. 1=Enable generation of a trap SMI for accesses to
the device monitor 3 enabled trap decode ranges. 0=Disable.
6 Device 3 Idle Enable (IDL_EN_DEV3)—R/W. 1=Enable the device monitor 3 idle reload events to
reload the device monitor 3 idle timer. 0=Disable.
5 Device 2 Trap Enable (TRP_EN_DEV2)—R/W. 1=Enable generation of a trap SMI for accesses to
the device monitor 2 enabled trap decode ranges. 0=Disable.
4 Device 2 Idle Enable (IDL_EN_DEV2)—R/W. 1=Enable the device monitor 2 idle reload events to
reload the device monitor 2 idle timer. 0=Disable.
3 Device 1 Trap Enable (TRP_EN_DEV1)—R/W. 1=Enable generation of a trap SMI for accesses to
the device monitor 1 enabled trap decode ranges. 0=Disable.
2 Device 1 Idle Enable (IDL_EN_DEV1)—R/W. 1=Enable the device monitor 1 idle reload events to
reload the device monitor 1 idle timer. 0=Disable.
1 Device 0 Trap Enable (TRP_EN_DEV0)—R/W. 1=Enable generation of a trap SMI for accesses to
the device monitor 0 enabled trap decode ranges. 0=Disable.
0 Device 0 Idle Enable (IDL_EN_DEV0)—R/W. 1=Enable the device monitor 0 idle reload events to
reload the device monitor 0 idle timer. 0=Disable.
7.2.15. GPIREG—GENERAL PURPOSE INPUT REGISTER (IO)
I/O Address:
Default Value:
Attribute:
Base + (30h, 31h, 32h)
XXh
Read Only (Byte reads only)
Bit
Description
23:22 Reserved.
21:0 General Purpose Input (GPI)—RO. Each bit directly represents the logical value on the pin. Some
of the GPI signals can be configured as another input signal. The value in this register of
a bit which is not configured as a GPI is indeterminate and may change randomly.
PRELIMINARY
147
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)