82371AB Datasheet, PDF (105/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
6.1.7. MLT—MASTER LATENCY TIMER REGISTER (FUNCTION 2)
Address Offset:
Default Value:
Attribute:
0Dh
00h
Read/Write
MLT is an 8-bit register that controls the amount of time (in terms of PCI clocks) the USB module can do
transactions on the PCI bus. The count value is an 8-bit quantity, however MLT[3:0] are reserved and assumed
to be 0 when determining the count value. MLT is used when the USB module becomes the PCI bus master and
is cleared and suspended when PIIX4 is not asserting FRAME#. When PIIX4 asserts FRAME#, the counter is
enabled and begins counting. If the serial bus module finishes its transaction before count is expired, the MLT
value is ignored. If the count expires before the transaction completes, PIIX4 initiates a transaction termination
as soon as the current transaction is completed. The number of clocks programmed in the MLT represents the
guaranteed time slice (measured in PCI clocks) allotted to PIIX4, after which it must surrender the bus as soon
as the current transaction is completed.
Bit
Description
7:4 Master Latency Counter Value. PIIX4 initiated PCI cycles (including multiple transactions) can last
indefinitely as long as PHLDA# remains active. However, if PHLDA# is negated after a transaction is
initiated, PIIX4 limits the duration of the transactions to the number of PCI bus clocks specified by
this field.
3:0 Reserved.
6.1.8. HEDT—HEADER TYPE REGISTER (FUNCTION 2)
Address Offset:
Default Value:
Attribute:
0Eh
00h
Read Only
This register identifies the Serial Bus module as a single function device.
Bit
Description
7:0 Device Type (DEVICET). 00. Multi-function device capability for PIIX4 is defined by the HEDT
register in Function 0.
6.1.9. INTLN—INTERRUPT LINE REGISTER (FUNCTION 2)
Address Offset:
Default Value:
Attribute:
3Ch
00h
Read/Write
Software programs this register with interrupt information concerning the Universal Serial Bus.
Bit
Description
7:0 Interrupt Line. The value in this register has no affect on PIIX4 hardware operations.
PRELIMINARY
105
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)