82371AB Datasheet, PDF (171/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
Single Channel Mask Register
To make the peripherals easier to implement, the Distributed DMA specification does not have the peripherals
implement the Single-Channel Mask Registers. Instead, a write to the Single Channel Mask register (which
encodes the channel number in the low two bits) causes write the Write All Masks Register (which has a
separate mask bit for each channel). The Distributed DMA peripheral uses bit 0 in the Write All Masks Register
for that particular channel.
Thus, when a write occurs to the Single Channel Mask register, PIIX4 examines the low two data bits to
determine the DMA channel number. This causes a write the peripheral at Base Pointer + channel # + Fh. The
data value (bit 0) for that write cycle is determined by data bit 2 of the original CPU write.
Clear Mask Register
To make the peripherals easier to implement, the Distributed DMA specification does not have the peripherals
implement the Clear Mask Command. Instead, a write to the Clear Mask Command register (which has a don’t
care data value causes writes to all the distributed channels associated with that 8237).
Thus, when a write occurs to the Clear Mask Command register, PIIX4 performs up to 4 writes to the Write All
Masks register (Base Pointer + channel # + Fh) with a data value of 0h.
If another PCI master attempts to read or write to one of the DMA controller’s registers while a Distributed DMA
cycle is in progress, that cycle will be retried until the PC DMA protocol completes. This prevents two
outstanding PC/PCI requests.
8.6. Interrupt Controller
PIIX4 provides an ISA-Compatible interrupt controller that incorporates the functionality of two 82C59 interrupt
controllers (Figure 5). The two controllers are cascaded, providing 13 external and three internal interrupts. The
master interrupt controller provides IRQ [7:0] and the slave interrupt controller provides IRQ [15:8]. The three
internal interrupts are used for internal functions only. IRQ0 is available to the user only when an external IO
APIC is enabled. IRQ2 is used to cascade the two controllers and is not available to the user. IRQ0 is used as a
system timer interrupt and is tied to Interval Timer 1, Counter 0. IRQ13 is connected internally to FERR#. The
remaining 13 interrupt lines (IRQ[15:14,12:3,1]) are available for external system interrupts. Edge or level sense
selection is programmable on an individual channel by channel basis.
The Interrupt unit also supports interrupt steering. PIIX4 can be programmed to allow the four PCI active low
interrupts (PIRQ[A:D]#) to be internally routed to one of 11 interrupts (IRQ[15:14,12:9,7:3]).
The Interrupt Controller consists of two separate 82C59 cores. Interrupt Controller 1 (CNTRL-1) and Interrupt
Controller 2 (CNTRL-2) are initialized separately and can be programmed to operate in different modes. The
default settings are: 80x86 Mode, Edge Sensitive (IRQ[0:15]) Detection, Normal EOI, Non-Buffered Mode,
Special Fully Nested Mode disabled, and Cascade Mode. CNTRL-1 is connected as the Master Interrupt
Controller and CNTRL-2 is connected as the Slave Interrupt Controller.
Note that IRQ13 is generated internally (as part of the coprocessor error support) by PIIX4. IRQ12/M is
generated internally (as part of the mouse support) when bit-4 in the XBCS is set to a 1. When set to a 0, the
standard IRQ12 function is provided and IRQ12 appears externally.
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