82371AB Datasheet, PDF (50/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
3.4. Power Management Configuration
The PIIX4 PCI function 3 contains enhanced Power Management logic with support for Device Management,
Suspend and Resume states, and System Clock Control. This function also supports a System Management
Bus (SMBus) Host and Slave interface. The register set associated with Power Management and SMBus
controller is shown below with actual register descriptions given in section 0.
Table 10. PCI CONFIGURATION REGISTERS (FUNCTION 3)
Address Offset Mnemonic
Register Name
00–01h
VID
Vendor Identification
02–03h
DID
Device Identification
04–05h
PCICMD
PCI Command
06–07h
PCISTS
PCI Device Status
08h
RID
Revision Identification
09−0Bh
CLASSC
Class Code
0C–0Dh
—
Reserved
0Eh
HEDT
Header Type
0F–3Bh
—
Reserved
3Ch
INTLN
Interrupt Line
3Dh
INTPN
Interrupt Pin
3E–3Fh
—
Reserved
40–43h
PMBA
Power Management Base Address
44–47h
CNTA
Count A
48–4Bh
CNTB
Count B
4C–4Fh
GPICTL
General Purpose Input Control
50–52h
DEVRESD
Device Resource D
53h
—
Reserved
54–57h
DEVACTA
Device Activity A
58–5Bh
DEVACTB
Device Activity B
5C–5Fh
DEVRESA
Device Resource A
60–63h
DEVRESB
Device Resource B
64–67h
DEVRESC
Device Resource C
68–6Ah
DEVRESE
Device Resource E
6Bh
—
Reserved
6C–6Fh
DEVRESF
Device Resource F
70–72h
DEVRESG
Device Resource G
73h
—
Reserved
74–77h
DEVRESH
Device Resource H
78–7Bh
DEVRESI
Device Resource I
Access
RO
RO
R/W
R/WC
RO
RO
—
RO
—
R/W
RO
—
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
—
R/W
R/W
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