82371AB Datasheet, PDF (196/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
Main
Memory
Byte 3
Byte 2
Byte 1
Byte 0
Memory Region Physical Base Address [31:1]
0
EOT
Reserved
Byte Count [15:01] 0
Memory
Region
Figure 8. Physical Region Descriptor Table Entry
ide_desc
Operation
To initiate a bus master transfer between memory and an IDE DMA slave device, the following steps are
required:
1. Software prepares a PRD Table in main memory. Each PRD is 8-bytes long and consists of an address
pointer to the starting address and the transfer count of the memory buffer to be transferred. In any given
PRD Table, two consecutive PRDs are offset by 8 bytes and are aligned on a 4-byte boundary.
2. Software provides the starting address of the PRD Table by loading the PRD Table Pointer Register. The
direction of the data transfer is specified by setting the Read/Write Control bit. Clear the Interrupt bit and
Error bit in the Status register.
3. Software issues the appropriate DMA transfer command to the disk device. This includes the total amount of
data to be transferred.
4. Engage the bus master function by writing a 1 to the Start bit in the Bus Master IDE Command Register for
the appropriate channel. The first entry in the PRD table is fetched by PIIX4. The channel remains masked
until the first descriptor is loaded.
5. The controller transfers data to or from memory responding to the DMA requests from the IDE device. When
the last data transfer for a memory region has been completed on the IDE interface, the next PRD is fetched
from the table. The controller then begins transferring data to or from that PRD’s memory region.
6. The IDE device signals an interrupt once its programmed data count has been transferred. The IDE device
will also negate its DMA request signal, causing PIIX4 to stop transferring data. If PIIX4 has also transferred
the final data from the last PRD memory region, it will reset the BMIDEA bit in the status register and mask
the DMA request signal from the drive.
7. In response to the interrupt, software resets the Start/Stop bit in the command register. It then reads the
controller status and then the drive status to determine if the transfer completed successfully. See the Bus
Master IDE Status Register section for a description of controller transfer status.
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