82371AB Datasheet, PDF (89/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
5.0. IDE CONTROLLER REGISTER DESCRIPTIONS (PCI FUNCTION 1)
This section describes in detail the registers associated with PIIX4 IDE Controller function. This includes
Programmed I/O (PIO), Bus Master, and “Ultra DMA/33” synchronous DMA functionality.
5.1. IDE Controller PCI Configuration Registers (PCI Function 1)
5.1.1. VID—VENDOR IDENTIFICATION REGISTER (FUNCTION 1)
Address Offset:
Default Value:
Attribute:
00–01h
8086h
Read Only
The VID Register contains the vendor identification number. This register, along with the Device Identification
Register, uniquely identify any PCI device. Writes to this register have no effect.
Bit
Description
15:0 Vendor Identification Number. This is a 16-bit value assigned to Intel.
5.1.2. DID—DEVICE IDENTIFICATION REGISTER (FUNCTION 1)
Address Offset:
Default Value:
Attribute:
02–03h
7111h
Read Only
The DID Register contains the device identification number. This register, along with the VID Register, define the
PIIX4 function. Writes to this register have no effect.
Bit
Description
15:0 Device Identification Number. This is a 16-bit value assigned to the PIIX4 IDE Controller function.
5.1.3. PCICMD—PCI COMMAND REGISTER (FUNCTION 1)
Address Offset:
Default Value:
Attribute:
04–05h
0000h
Read/Write
The PCICMD Register controls access to the I/O space registers.
Bit
Description
15:10 Reserved. Read 0.
9 Fast Back to Back Enable (FBE) (Not Implemented). This bit is hardwired to 0.
8:5 Reserved. Read as 0.
4 Memory Write and Invalidate Enable (Not Implemented). This bit is hardwired to 0.
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