82371AB Datasheet, PDF (217/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
11.3.5.4.
Device 3: IDE Secondary Drive 1
Device 3 monitors the Secondary IDE device, drive 1 and GPI0. The IDE device DRV bit (bit 4 of port
176h) is shadowed to determine if drive 1 is active on the secondary connector. Device 3 can also be
used as a Software SMI# Timer. It has a configuration bit to disable the Idle Timer Reload so that the
timer can be allowed to expire based only on the timer count.
Device 3 System Events:
— PCI accesses to IO address 170–177h, 376h, independent of IDE enable in PCI
function 1, if secondary IDE drive 1 is active. This can cause idle, burst, or global
standby timer reloads or IO trap SMI#.
— SDDACK# assertion if secondary IDE drive 1 is active, the IDE interface is configured
as primary and secondary and BMIDE is active for secondary channel. This can cause
only idle, burst, and global standby timer reloads.
— Assertion of GPI0. The polarity of active signal (high or low) is selectable. This can
cause idle, burst, or global standby timer reloads or IO trap SMI#.
Device 3 Idle Timer:
Resolution: 1 msec or 8 sec
Count: 4 bit
GPI Enable:
GPI Polarity Select:
Device 3 Idle Timer Reload:
Idle Timer Reload Disable (SW):
Global Standby Timer Reload:
Burst Timer Reload:
Fast or Slow Burst Select:
Idle Timer Expiration SMI#:
Trap SMI#:
[IDL_SEL_DEV3]
[SW_CNT]
[GPI_EN_DEV3]
[GPI_POL_DEV3]
[IDL_EN_DEV3]
[IDL_RLD_EN_DEV3]
[GRLD_EN_DEV3]
[BRLD_EN_DEV3]
[BRLD_SEL_DEV3]
[IDL_EN_DEV3] [IDL_STS_DEV3]
[TRP_EN_DEV3] [TRP_STS_DEV3]
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