82371AB Datasheet, PDF (145/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
7.2.13. GLBCTL—GLOBAL CONTROL REGISTER (IO)
I/O Address:
Default Value:
Attribute:
Base + (28h)
00h
Read/Write
Bit
Description
31:27 Reserved.
26 Global Standby Timer Clocking Select B (GSTBY_SELB)—R/W. This bit in conjunction with
bit 8 selects the clock source for the Global Standby Timer. See bit 8 description for timing
programming combinations.
25 Lid Polarity (LID_POL)—R/W. 1=Active low LID assertion sets the LID_STS bit. 0=Active high LID
assertion sets the LID_STS bit.
24 System Management Freeze (SM_FREEZE)—R/W. 1=Disable all Device Monitor idle timers and
the Global Standby Timer from counting. 0=Enable timers to count.
23:17 Reserved.
16 End of SMI (EOS)—R/W. 1=Enable PIIX4 to assert an SMI#. 0=Disable. This bit is cleared
automatically upon generation of an SMI#.
15:9 Global Standby Timer Initial Count (GSTBY_CNT)—R/W. Specifies the initial and reload count of
the Global Standby Timer.
8 Global Standby Timer Clocking Select A (GSTBY_SELA)—R/W. This bit in conjunction with bit
26 selects the clock source for the Global Standby Timer.
Bits[26,8]
0,0
0,1
1,0
1,1
Clock Rate
32 seconds (default)
4 minutes
4 milliseconds
4 seconds
7:3 Reserved.
2 Thermal Polarity (THRM_POL)—R/W. 1=Active low THRM# assertion sets the THRM_STS bit.
0=Active high THRM# assertion sets the THRM_STS bit.
1 BIOS Release (BIOS_RLS)—R/W. 1=A 1 written to this bit position causes an SCI to be generated
and GBL_STS bit set, if enabled by the GBL_EN bit. 0=No SCI generated. This bit is used by the
BIOS software to raise an event to the ACPI software. This bit always reads a 0.
0 SMI ENABLE (SMI_EN)—R/W. 1=Enable the generation of SMI# upon any enabled SMI# event.
0=Disable. This bit is reset by a PCI reset event.
PRELIMINARY
145
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)