82371AB Datasheet, PDF (96/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
5.1.12. UDMACTL—ULTRA DMA/33 CONTROL REGISTER (FUNCTION 1)
Address Offset:
Default Value:
Attribute:
48h
00h
Read/Write
This register enables each individual channel and drive for Ultra DMA/33 operation. For non-Ultra DMA/33
operation, this register should be left programmed to its default value.
Bit
Description
7:4 Reserved.
3 Secondary Drive 1 UDMA Enable (SSDE1). 1=Enable Ultra DMA/33 mode for secondary channel
drive 1. 0=Disable (default).
2 Secondary Drive 0 UDMA Enable (SSDE0). 1=Enable Ultra DMA/33 mode for secondary channel
drive 0. 0=Disable (default).
1 Primary Drive 1 UDMA Enable (PSDE1). 1=Enable Ultra DMA/33 mode for primary channel drive
1. 0=Disable (default).
0 Primary Drive 0 UDMA Enable (PSDE0). 1=Enable Ultra DMA/33 mode for primary channel drive
0. 0=Disable (default).
5.1.13. UDMATIM—ULTRA DMA/33 TIMING REGISTER (FUNCTION 1)
Address Offset:
Default Value:
Attribute:
4A–4Bh
00h
Read/Write Only
This register controls the timings used by each Ultra DMA/33 enabled device. For non-Ultra DMA/33 operation,
this register should be left programmed to its default value.
96
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