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82371AB Datasheet, PDF (132/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4
82371AB (PIIX4)
E
Bit
Description
14:8 Reserved.
7 Device 12 Memory Monitor Enable (MEM_EN_DEV12)—R/W. 1=Enable PCI bus decode for
accesses to the memory address range selected by the MBASE_DEV12 and MMASK_DEV12
fields. 0=Disable. The EIO enable bit, or trap enable bit for device 12 must also be set in order to
enable these respective functions.
6:0 Device 12 Memory Decode Mask (MMASK_DEV12)—R/W. Specifies the 7-bit memory base
address mask used to determine the memory address range size for device 12 accesses.
MMASK_DEV12 (bits[6:0]) correspond to AD[21:15]. A ‘1’ in a bit position indicates that the
corresponding address bit is masked (i.e. ignored) when performing the decode. Note that
programming these bits to certain patterns (such as ‘1110011’) results in split address ranges.
7.1.22. DEVRESG—DEVICE RESOURCE G (FUNCTION 3)
Address Offset:
Default Value:
Attribute:
70–72h
00h
Read/Write
Bit
Description
23:21 Reserved.
20 Device 13 I/O Monitor Enable (IO_EN_DEV13)—R/W. 1=Enable PCI bus decode for accesses to
the I/O address range selected by the IBASE_DEV13 and IMASK_DEV13 fields. 0=Disable. The
EIO enable bit or trap enable bit for device 13 must also be set in order to enable these respective
functions.
19:16
I/O Decode Mask (IMASK_DEV13)—R/W. Specifies the 4-bit I/O base address mask used to
determine the IO address range size for device 13 accesses. IMASK_DEV13 (bits[19:16])
correspond to AD[3:0]. A ‘1’ in a bit position indicates that the corresponding address bit is masked
(i.e. ignored) when performing the decode. Note that programming these bits to certain patterns
(such as ‘1001’) results in a split address range.
15:0 I/O Decode Base Address (IBASE_DEV13)—R/W. Specifies the 16-bit I/O base address range
(AD[15:0]) for the device 13 I/O range. When this field is combined with IMASK_DEV13 field, an I/O
range is defined starting from the base address register value to the size defined by the mask
register.
132
PRELIMINARY
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)