82371AB Datasheet, PDF (118/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
Bit
Description
3 Special Cycle Enable (Not Implemented). This bit is hardwired to 0.
2 Bus Master Enable (Not Implemented). This bit is hardwired to 0.
1 Memory Space Enable (Not Implemented). This bit is hardwired to 0.
0 I/O Space Enable (IOSE). 1=Enable. 0=Disable. This bit controls the access to the SMBus I/O
space registers whose base address is described in the SMBus Base Address register. If this bit is
set, access to the SMBus IO registers is enabled. The base register for the I/O registers must be
programmed before this bit is set. When disabled, all IO accesses associated with SMBus Base
Address are disabled. This bit functions independent of the state of Function 3 Power Management
IO Space Enable (PMIOSE) bit (PMREGMISC register, bit 0).
7.1.4. PCISTS—PCI DEVICE STATUS REGISTER (FUNCTION 3)
Address Offset:
Default Value:
Attribute:
06−07h
0280h
Read/Write
DSR is a 16-bit status register that reports the occurrence of a PCI target-abort when the Power Management
function is a target device. The register also indicates the Power Management DEVSEL# signal timing that is
hardwired in the module.
Bit
Description
15 Detected Parity (Not Implemented). This bit is hardwired to 0.
14 SERR# Status (Not Implemented). This bit is hardwired to 0.
13 Master-Abort Status (Not Implemented). This bit is hardwired to 0.
12 Received Target-Abort Status (Not Implemented). This bit is hardwired to 0.
11 Signaled Target-Abort Status (STA)—R/WC. This bit is set when the Power Management function
is targeted with a transaction that it terminates with a target abort. Software resets STA
to 0 by writing a 1 to this bit.
10:9 DEVSEL# Timing Status (DEVT)—RO. This 2-bit field defines the timing for DEVSEL# assertion.
These read only bits indicate PIIX4’s DEVSEL# timing when performing a positive decode. Since
PIIX4 always generate the DEVSEL# with medium timing, DEVT=01. This DEVSEL# timing does not
include Configuration cycles.
8 Data Parity Detected (Not Implemented). This bit is hardwired to 0.
7 Fast Back to Back Capable (FBC)—RO. Hardwired to 1. This bit indicates to the PCI Master that
Power Management as a target is capable of accepting fast back-to-back transactions.
6:0 Reserved. Read as 0’s.
118
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