82371AB Datasheet, PDF (109/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
6.1.14. MISCSUP—MISCELLANEOUS SUPPORT REGISTER (FUNCTION 2)
Address Offset:
Default Value:
Attribute:
FFh
XXh
Read/Write (Byte accesses only)
This register provides miscellaneous control capability for the PIIX4. The following programming model must be
followed to read the RTC Index register.
1. Disable USB.
2. Read MISCSUP register.
3. Change the RTC Index Read Enable bit to 1 without changing the other register bits.
4. Write new value to MISCSUP register location.
5. Read the RTC Index register at I/O location 70h. Only bits [6:0] provide RTC Index value. Bit 7 is
indeterminate.
6. Read the MISCSUP register.
7. Change the RTC Index Read Enable bit to 0 without changing the other register bits.
8. Write new value to MISCSUP register location.
9. Re-enable USB as desired.
Bit
Description
7:5 Undefined. Hardwired to 0s. Must be written as 0s.
4 RTC Index Read Enable (RTCIREN). 1=Enable reads to IO address 70h to return the value located
in the RTC Index register. 0=Disable.
3:0 Undefined. Read as 0.
6.2. USB Host Controller IO Space Registers
6.2.1. USBCMD—USB COMMAND REGISTER (IO)
I/O Address:
Default Value:
Attribute:
Base + (00−01h)
0000h
Read/Write (Word writeable only)
The Command Register indicates the command to be executed by the serial bus host controller. Writing to the
register causes a command to be executed. The table following the bit description provides additional information
on the operation of the Run/Stop and Debug bits.
Bit
Description
15:8 Reserved.
7 Max Packet (MAXP). 1=64 bytes. 0=32 bytes. This bit selects the maximum packet size that can be
used for full speed bandwidth reclamation at the end of a frame. This value is used by the Host
Controller to determine whether it should initiate another transaction based on the time remaining in
the SOF counter. Use of reclamation packets larger than the programmed size will cause a Babble
error if executed during the critical window at frame end. The Babble error results in the offending
endpoint being stalled. Software is responsible for ensuring that any packet which could be executed
under bandwidth reclamation be within this size limit.
PRELIMINARY
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INTEL CONFIDENTIAL
(until publication date)