82371AB Datasheet, PDF (110/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
Bit
Description
6 Configure Flag (CF). HCD software sets this bit as the last action in its process of configuring the
Host Controller. This bit has no effect on the hardware. It is provided only as a semaphore service
for software.
5 Software Debug (SWDBG). 1=Debug mode. 0=Normal Mode. In SW Debug mode, the Host
Controller clears the Run/Stop bit after the completion of each USB transaction. The next transaction
is executed when software sets the Run/Stop bit back to 1. The SWDBG bit must only be
manipulated when the controller is in the stopped state. This can be determined by checking the
HCHalted bit in the USBSTS register.
4 Force Global Resume (FGR). 1=Host Controller sends the Global Resume signal on the USB.
Software sets this bit to 0 after 20 ms has elapsed to stop sending the Global Resume signal. At that
time all USB devices should be ready for bus activity. The Host Controller sets this bit to 1 when a
resume event (connect, disconnect, or K-state) is detected while in global suspend mode. Software
resets this bit to 0 to end Global Resume signaling. The 1 to 0 transition causes the port to send a
low speed EOP signal. This bit will remain a 1 until the EOP has completed.
3 Enter Global Suspend Mode (EGSM). 1=Host Controller enters the Global Suspend mode. No
USB transactions occurs during this time. The Host Controller is able to receive resume signals from
USB and interrupt the system. Software resets this bit to 0 to come out of Global Suspend mode.
Software writes this bit to 0 at the same time that Force Global Resume (bit 4) is written to 0 or after
writing bit 4 to 0. Software must also ensure that the Run/Stop bit (bit 0) is cleared prior to setting this
bit.
2 Global Reset (GRESET). When this bit is set, the Host Controller sends the global reset signal on
the USB and then resets all its logic, including the internal hub registers. The hub registers are reset
to their power on state. This bit is reset by the software after a minimum of 10 ms has elapsed as
specified in Chapter 7 of the USB Specification.
Note: Chip Hardware Reset has the same effect as Global Reset (bit 2), except that the Host
Controller does not send the Global Reset on USB.
1 Host Controller Reset (HCRESET). When this bit is set, the Host Controller module resets its
internal timers, counters, state machines, etc. to their initial value. Any transaction currently in
progress on USB is immediately terminated. This bit is reset by the Host Controller when the reset
process is complete.
The HCReset effects on Hub registers are slightly different from Chip Hardware Reset and Global
USB Reset. The HCReset affects bits [8,3:0] of the Port Status and Control Register (PORTSC) of
each port. HCReset resets the state machines of the Host Controller including the
Connect/Disconnect state machine (one for each port). When the Connect/Disconnect state
machine is reset, the output that signals connect/disconnect are negated to 0, effectively signaling a
disconnect, even if a device is attached to the port. This virtual disconnect causes the port to be
disabled. This disconnect and disabling of the port causes bit 1 (connect status change) and bit 3
(port enable/disable change) of the PORTSC to get set. The disconnect also causes bit 8 of
PORTSC to reset. About 64-bit times after HCReset goes to 0, the connect and low-speed detect
will take place and bits 0 and 8 of the PORTSC will change accordingly.
0 Run/Stop (RS). 1=Run. 0=Stop. When set to a 1, the Host Controller proceeds with execution of the
schedule. The Host Controller continues execution as long as this bit is set. When this bit is set to 0,
the Host Controller completes the current transaction on the USB and then halts. The
HCHalted bit in the status register indicates when the Host Controller has finished the transaction
and has entered the stopped state. The Host Controller clears this bit when the following fatal errors
occur: consistency check failure, PCI Bus errors.
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PRELIMINARY
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
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