82371AB Datasheet, PDF (131/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
Bit
Description
19:16
Device 10 Generic Decode Mask (MASK_DEV10)—R/W. Specifies the 4-bit I/O base address
mask used to determine the IO address range size for device 10 accesses. MASK_DEV10
(bits[19:16]) correspond to AD[3:0]. A ‘1’ in a bit position indicates that the corresponding address bit
is masked (i.e. ignored) when performing the decode. Note that programming these bits to certain
patterns (such as ‘1001’) results in a split address range.
15:0 Device 10 Generic Decode Base Address (BASE_DEV10)—R/W. Specifies the 16-bit I/O base
address range (AD[15:0]) for the device 10 I/O range. When this field is combined with
MASK_DEV10 field, an I/O range is defined starting from the base address register value to the size
defined by the mask register.
7.1.20. DEVRESE—DEVICE RESOURCE E (FUNCTION 3)
Address Offset:
Default Value:
Attribute:
68–6Ah
00h
Read/Write
Bit
Description
23:21 Reserved.
20 Device 12 I/O Monitor Enable (IO_EN_DEV12)—R/W. 1=Enable PCI bus decode for accesses to
the I/O address range selected by the IBASE_DEV12 and IMASK_DEV12 fields. 0=Disable. The
EIO enable bit, or trap enable bit for device 12 must also be set in order to enable these respective
functions.
19:16
Device 12 I/O Decode Mask (IMASK_DEV12)—R/W. Specifies the 4-bit I/O base address mask
used to determine the IO address range size for device 12 accesses. IMASK_DEV12 (bits[19:16])
correspond to AD[3:0]. A ‘1’ in a bit position indicates that the corresponding address bit is masked
(i.e. ignored) when performing the decode. Note that programming these bits to certain patterns
(such as ‘1001’) results in a split address range.
15:0 Device 12 I/O Decode Base Address (IBASE_DEV12)—R/W. Specifies the 16-bit I/O base
address range (AD[15:0]) for the device 12 I/O range. When this field is combined with
IMASK_DEV12 field, an I/O range is defined starting from the base address register value to the size
defined by the mask register.
7.1.21. DEVRESF—DEVICE RESOURCE F (FUNCTION 3)
Address Offset:
Default Value:
Attribute:
6C–6Fh
00h
Read/Write
Bit
Description
31:15
Device 12 Memory Decode Base Address (MBASE_DEV12)—R/W. Specifies the 17-bit memory
base address range (AD[31:15]) for the device 12 memory range. When this field is combined with
the MMASK_DEV12 field, a memory range is defined from the base address value to the size
defined by the mask register.
PRELIMINARY
131
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(until publication date)