82371AB Datasheet, PDF (168/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
Table 23. PCI Data Bus vs. DMA I/O port size
PCI DMA I/O Port Size
PCI Data Bus Connection
Word
AD[15:0]
Table 24. DMA I/O Cycle Width vs. BE[3:0]#
BE[3:0]#
Description
1110b
8-bit DMA I/O Cycle
1100b
16-bit DMA I/O Cycle
NOTES:
For verify cycles the value of the Byte Enables (BEs) is a “don’t care.”
Every DMA device (including Secondary Bus Arbiters) must recognize a valid signal on its GNT# combined with
the DMA I/O address as its command authorization to initiate a DMA access cycle. PIIX4 is required to assert
the DMA I/O device’s GNT# signal until the data phase of the I/O portion of the DMA transfer.
8.5.2. DISTRIBUTED DMA
The Distributed DMA (DDMA) scheme is based on the concept that the registers associated with individual DMA
can physically reside outside of PIIX4, specifically on other PCI devices. The Distributed DMA logic in PIIX4 is
only used when the CPU does accesses to the 8237 registers. Data movement is the responsibility of the
peripheral.
Separate algorithms are followed depending whether the CPU attempts a read cycle or write cycle. Each is
covered separately. PIIX4 is able to determine if a particular DMA channel is “distributed” based on the PCI
configuration space.
Additional Configuration
PIIX4 contains two registers to indicate the I/O locations for the relocated DMA registers for the DDMA
peripherals. The first register indicates the offset of the registers associated with DMA channels 0–3. The
second indicates the offset of the registers associated with DMA channels 5–7. Channel 4 is assumed to be
unavailable. It is up to the BIOS or other configuration software to program the DDMA peripherals to the
corresponding locations.
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