82371AB Datasheet, PDF (135/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
7.1.27. SMBBA—SMBUS BASE ADDRESS (FUNCTION 3)
Address Offset:
Default Value:
Attribute:
90−93h
00000001h
Read/Write
This register contains the base address of the SMBus I/O Registers.
Bit
Description
31:16 Reserved. Hardwired to 0s. Must be written as 0s.
15:4 Index Register Base Address. Bits [15:4] correspond to I/O address signals AD [15:4],
respectively.
3:1 Reserved. Read as 0.
0 Resource Type Indicator (RTE)—RO. This bit is hardwired to 1 indicating that the base address
field in this register maps to I/O space.
7.1.28. SMBHSTCFG—SMBUS HOST CONFIGURATION (FUNCTION 3)
Address Offset:
Default Value:
Attribute:
D2h
00h
Read/Write
Bit
Description
7:4 Reserved.
3:1 SMBus Interrupt Select (SMB_INTRSEL)—R/W. Selects the type of interrupt generated by the
SMBus controller. This field is decoded as follows:
Bits[3:1]
000
001
010
011
SMBus Interrupt
SMI#
Reserved
Reserved
Reserved
Bits[3:1]
100
101
110
111
SMBus Interrupt
IRQ9
Reserved
Reserved
Reserved
0 SMBus Controller Host Interface Enable (SMB_HST_EN)—R/W. 1=Enable the SMBus Controller
Host Interface. 0=Disable.
7.1.29. SMBSLVC—SMBUS SLAVE COMMAND (FUNCTION 3)
Address Offset:
Default Value:
Attribute:
D3h
00h
Read/Write
Bit
Description
7:0 SMBus Host Slave Command (SMBCMD)—R/W. Specifies the command values to be matched
for SMBus master accesses to the SMBus controller host slave interface (SMBus port 10h).
PRELIMINARY
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