82371AB Datasheet, PDF (266/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
11.5.4. SMBUS FUNCTIONAL DESCRIPTION
The System Management Bus (SMBus) is a two-wire interface through which the system can communicate with
simple power-related chips. With SMBus, a device can provide manufacturer information, indicate its model/part
number, save its state for a suspend event, report different types of errors, accept control parameters, and return
status.
PIIX4 provides a SMBus host controller, host controller slave port, and two SMBus slave shadow ports. The
SMBus host controller provides a mechanism for the processor to initiate communications with SMBus
peripherals. This can be used to configure system devices or to query devices for status. The SMBus slave
interface provides a mechanism for other SMBus masters to communicate with PIIX4 and can be used to
generate interrupts or resume events for a suspended system. PIIX4 also supports the SMBus ALERT#
protocol. PIIX4’s SMBus controller has 3.3V input buffers, which requires the system’s SMBus to be designed
with a 3.3V termination voltage. The programming model is split between function 3 PCI configuration registers
and SMBus I/O space registers.
The System Management Bus is a subset of the Phillips* I²C* protocol.
SMB
Host
Controller
SMB Slave Interface
- Host Slave
- Shadow Ports
smbus
Figure 32. SMBus Interface
11.5.4.1.
SMBus Host Interface
A SMBus Host Controller is used to send commands to various SMBus devices. The PIIX4 SMBus controller
implements a full host controller implementation. The PIIX4 SMBus controller supports seven command
protocols of the SMBus interface (see System Management Bus Specification, Revision 1.0): Quick Command,
Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Block Read, and Block Write.
To execute a SMBus host transaction, the type of transfer protocol, the address of SMBus device, the device
specific command, the data, and any control bits are first setup. Then the START bit is set, which causes the
host controller to execute the transaction. When the transaction is completed, PIIX4 generates an interrupt, if
enabled. The interrupt can be selected between IRQ9 or SMI#. The system software can wait for interrupt to
signal completion or it can monitor the HOST_BUSY status bit. An interrupt is also signaled if an error
occurred during the transaction or if the transaction was terminated by software setting the KILL bit. The
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