82371AB Datasheet, PDF (197/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
Line Buffer
A single line buffer exists for the PIIX4 Bus master IDE interface. This buffer is not shared with any other
function. The buffer is maintained in either the read state or the write state. Memory writes are typically
4-DWord bursts and invalid DWords have C/BE[3:0]#=0Fh. The line buffer allows burst data transfers to proceed
at peak transfer rates.
The Bus Master IDE Active bit in Bus Master IDE Status register is reset automatically when the controller has
transferred all data associated with a Descriptor Table (as determined by EOT bit in last PRD). The IDE Interrupt
Status bit is set when the IDE device generates an interrupt. These events may occur prior to line buffer
emptying for memory writes. If either of these conditions exist, all PCI Master non-memory read accesses to
PIIX4 are retried until all data in the line buffers has been transferred to memory.
Bus Master IDE Timings
The timing modes used for Bus Master IDE transfers are identical to those for PIO transfers. The DMA Timing
Enable Only bits in IDE Timing register can be used to program fast timing mode for DMA transactions only. This
is useful for IDE devices whose DMA transfer timings are faster that its PIO transfer timings.
The IDE device DMA request signal is sampled on same PCI clock that the IO strobe is negated. If inactive, the
DMA Acknowledge signal is negated on the next PCI clock and no more transfers take place until DMA request
is again asserted.
9.5. “Ultra DMA/33” Synchronous DMA Operation
Ultra DMA/33 is a new physical protocol used to transfer data between an Ultra DMA/33 capable IDE controller
such as PIIX4 and one or more Ultra DMA/33 capable IDE devices. It utilizes the standard Bus Master IDE
functionality and interface to initiate and control the transfer. Ultra DMA/33 utilizes a “source synchronous”
signaling protocol to transfer data at rates up to 33 Mbytes/sec. The Ultra DMA/33 definition also incorporates a
Cyclic Redundancy Checking (CRC-16) error checking protocol. CRC-16 only has the ability for detecting errors,
not correcting them.
Signal Descriptions
The Ultra DMA/33 protocol requires no extra signal pins on the IDE connector. It does redefine a number of the
standard IDE control signals when in Ultra DMA/33 mode. These redefinitions are shown in Table 31. Read
cycles are defined as transferring data from the IDE device to PIIX4. Write cycles are defined as transferring
data from PIIX4 to IDE device.
Standard IDE
Signal Definition
DIOW#
DIOR#
IORDY
Table 31. Ultra DMA/33 Control Signal Redefinitions
Ultra DMA/33 Read Ultra DMA/33 Write PIIX4 Primary
Cycle Definition Cycle Definition Channel Signal
STOP
STOP
PDIOW#
DMARDY#
STROBE
PDIOR#
STROBE
DMARDY#
PIORDY
PIIX4 Secondary
Channel Signal
SDIOW#
SDIOR#
SIORDY
The DIOW# signal is redefined as STOP for both read and write transfers. This is always driven by PIIX4 and is
used to request that a transfer be stopped or as an acknowledgment to stop a request from IDE device.
PRELIMINARY
197
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)