82371AB Datasheet, PDF (212/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
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11.3.2. DEVICE TRAP
Each device monitor can enable an IO Trap so that when software makes an access to the enabled I/O or
memory range a Trap Status bit is set and an SMI# is generated if enabled. The I/O trap SMI# is synchronous to
the completion of the I/O instruction in the processor. The I/O instruction is completed when the BRDY# is
returned to the processor. PIIX4 coordinates the assertion of SMI# to the processor with the generation of
BRDY# to the processor from the Host Bridge such that the SMI# is generated at least
3 HCLKs before Ready is generated. This allows the processor to perform an IO restart cycle. If the device to be
trapped is a PCI device, PIIX4 must be enabled to claim the cycle so that the SMI# can be generated
synchronously. The device should be programmed to send the I/O access cycle to the ISA bus where it is
terminated normally (although read cycles will return unknown data).
11.3.3. PERIPHERAL DEVICE MANAGEMENT SEQUENCE
Following is a brief description of the peripheral device power management process.
• Setup: The system’s power management software initializes the access I/O address ranges and the Idle
Timer counter for each peripheral device.
• On-to-Off Transition: When power management software enables the Idle Timer for that device, the Idle
Timer begins to count down. Any access to a peripheral device’s I/O address (also DACK# or GPI assertion
if enabled) reloads that device’s Idle Timer. If the peripheral device’s Idle Timer expires, the Idle Status bit is
set, and an SMI# is generated. The power management software (SMI# handler) identifies the device by the
status bit, then puts the peripheral device into a low power state, disables the Idle Timer hardware, and
enables the I/O Trap hardware.
• Off-to-On Transition: When the system requires an I/O access to that device range, the access is trapped,
an SMI# is generated, and the corresponding I/O Trap SMI status bit is set. The power management
software determines which device was accessed, restores the peripheral device to the “on” state, clears the
Trap SMI status bits, and then enables the Idle Timer hardware. The processor then issues an I/O restart to
access the device again.
11.3.4. DEVICE LOCATION ON PCI BUS OR ISA BUS
Most of the peripheral devices have the capability to exist on the PCI Bus or the ISA/EIO Bus. However, PIIX4
does not support RTC or Keyboard Controller to be resided on the PCI Bus. The Device Activity Monitor is
watching cycles on the PCI bus to generate activity events. The device monitors also can be enabled to forward
cycles to the device’s enabled addresses to the ISA bus. Devices that reside on the ISA Bus must have both
address ranges selected and enabled AND the ISA/EIO forwarding enabled.
PCI accesses to external IDE devices on the PCI bus do not generate power management events (Idle timer
reloads, global standby timer reloads, burst timer reloads, I/O traps). Power management of external
PCI-based IDE devices must use other means to monitor the activity of those devices. On next page are the
following methods for system BIOS to use to monitor external PCI-based IDE devices:
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PRELIMINARY
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