82371AB Datasheet, PDF (40/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
2.2. Power Planes
PIIX4 has three primary internal power planes. These power planes permit parts of PIIX4 to power down to
conserve battery life. Table 3 shows the internal planes and their uses.
Table 3. PIIX4 Internal Power Planes
Power
Plane
Description
Signals Powered
VCC GND
Pins Pins
RTC
Contains the real-time clock and 256 bytes of
battery-backed SRAM. This plane is always
powered if the internal RTC is used. If the internal
RTC is not used, it may be connected
to the suspend plane. Typically, powered via
“coin-cell” lithium battery.
PWROK, RSMRST#,
RTCX1, RTCX2
VCC
VSS
(RTC)
The input signals attached to the RTC power
plane DO NOT SUPPORT 5 VOLT INPUT
LEVELS. These signals must not exceed VCC
(RTC).
There is no reset signal for this power plane.
SUSPEND Contains the logic needed to resume from the
BATLOW#,
VCC
VSS
Suspend-to-Disk and Suspend-to-RAM states. CONFIG[1:2], EXTSMI# (SUS)
This plane will typically be powered by a power GPI1, GPO8, IRQ8#,
supply which is capable of providing a “trickle”
LID, RI#
current.
SMBALERT#, SMBCLK
The input signals attached to the SUSPEND
power plane DO NOT SUPPORT 5 VOLT INPUT
LEVELS. These signals must not exceed VCC
(SUS).
SMBDATA, PWRBTN#
SUS[A:C]#, SUSCLK
SUS_STAT[1:2]#,
TEST#
This plane is reset by assertion of the RSMRST#
signal.
USB
Contains the USB input/output buffers.
USBP0+, USBP0–
USBP1+, USBP1–
VCC
VSS
(USB) (USB)
Core
Contains all the rest of the PIIX4 logic. This plane
is powered by the main system power supply. All
input signals within this plane are 5V tolerant
except FERR#. This plane is reset by negation of
the PWROK signal.
All Other Signal Pins
VCC
VSS
40
PRELIMINARY
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)