82371AB Datasheet, PDF (148/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
7.2.16. GPOREG—GENERAL PURPOSE OUTPUT REGISTER (IO)
I/O Address:
Default Value:
Attribute:
Base + (34h, 35h, 36h, 37h)
7FFFBFFFh
Read/Write (Byte accesses only)
Bit
Description
31 Reserved.
30:0 General Purpose Output (GPO)—R/W. Each bit directly represents the logical value output onto
the pin. Reads to this register return the last value written. Some GPO signals can be configured as
another output signal. In that case, the output pin will not reflect the state of the corresponding GPO
bit in this register. Some of the output signals default to another signal.
7.3. SMBus IO Space Registers
The “Base” address is programmed in the PIIX4 PCI Configuration Space for Function 3 (Offset 90h–93h).
7.3.1. SMBHSTSTS—SMBUS HOST STATUS REGISTER (IO)
I/O Address:
Default Value:
Attribute:
Base + (00h)
00h
Read/Write
This register provides status information concerning the SMBus controller host interface.
Bit
Description
7:5 Reserved.
4 Failed (FAILED)—R/WC. 1=Indicates that the source of SMBus interrupt was a failed bus
transaction, set when KILL bit is set (SMBHSTCNT register). 0=SMBus interrupt not caused by KILL
bit. This bit is only set by hardware and can only be reset by writing a 1 to this bit position.
3 BUS COLLISION (BUS_ERR)—R/WC. 1=Indicates that the source of SMBus interrupt was a
transaction collision. 0=SMBus interrupt not caused by transaction collision. This bit is only set by
hardware and can only be reset by writing a 1 to this bit position.
2 Device Error (DEV_ERR)—R/WC. 1=Indicates that the source of SMBus interrupt was the
generation of an SMBus transaction error. 0=SMBus interrupt not caused by transaction error. This
bit is only set by hardware and can only be reset by writing a 1 to this bit position. Transaction errors
are caused by:
• Illegal Command Field
• Unclaimed Cycle (host initiated)
• Host Device Time-out
1 SMBus Interrupt (INTER)—R/WC. 1=Indicates that the source of SMBus interrupt was the
completion of the last host command. 0=SMBus interrupt not caused by host command completion.
This bit is only set by hardware and can only be reset by writing a 1 to this bit position.
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