82371AB Datasheet, PDF (84/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
4.2.4.2.
NMIEN—NMI Enable Register (Shared with Real-Time Clock Index Register) (IO)
I/O Address:
Default Value:
Attribute:
070h
Bit[6:0]=undefined; Bit 7=1
Write Only
This port is shared with the real-time clock. Do not modify the contents of this register without considering the
effects on the state of the other bits. Reads and writes to this register address flow through to the ISA Bus.
Reads to register 70h will cause X-Bus reads, but no RTCCS# or RTCALE will be generated. (The RTC has
traditionally been write-only to port 70h.)
Bit
Description
7 NMI Enable. 1=Disable generation of NMI; 0=Enable generation of NMI.
6:0 Real Time Clock Address. Used by the Real Time Clock to address memory locations. Not used
for NMI enabling/disabling.
4.2.5. REAL TIME CLOCK REGISTERS
4.2.5.1.
RTCI—Real-Time Clock Index Register (Shared with NMI Enable Register) (IO)
I/O Address:
Default Value:
Attribute:
070h
Bit[6:0]=Undefined; Bit 7=1
Write Only
This port is shared with the NMI enable. Do not modify the contents of this register without considering the
effects on the state of the other bits. Reads and writes to this register address flow through to the ISA Bus.
Reads to register 70h will cause X-Bus reads, but no RTCCS# or RTCALE will be generated. (The RTC has
traditionally been write-only to port 70h.)
Bit
Description
7 NMI Enable. Used by PIIX4 NMI logic.
6:0 Real Time Clock Address. Latched by the Real Time Clock to address memory locations within the
standard RAM bank accessed via the Real Time Clock Data Register (071h).
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