82371AB Datasheet, PDF (226/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
11.3.5.13. Device 12: Cardbus Slot (or Generic I/O and MEM Device)
Device 12 monitors a generic I/O device or Memory device with a programmable IO or memory
address or GPI20. Its operation is the same as Device 13.
Device 12 System Events:
— PCI accesses to programmable IO addresses and memory addresses, selectable
below. This can cause burst, or global standby timer reloads, IO trap SMI#, or
forwarding of the cycle from PCI to ISA. The IO address consists of a 16-bit base
address and 4-bit mask, allowing an IO address range from 1 to 16 bytes. The memory
address consists of a 17-bit base address (AD[31:15]) and a 7-bit mask (AD[21:15]).
This provides memory ranges from 32 Kbytes to 4 Mbytes in size.
— Assertion of GPI20. The polarity of active signal (high or low) is selectable. It can also
be enabled as edge-triggered. This can cause burst, or global standby timer reloads or
IO trap SMI#.
— There is no idle timer associated with Device 12.
Device 12 IO Address Range:
[IO_EN_DEV12]
Programmable IO Base Address:
[IBASE_DEV12]
Programmable IO Mask:
[IMASK_DEV12]
Device 12 Memory Address Range:
[MEM_EN_DEV12]
Programmable Mem Base Addr:
[MBASE_DEV12]
Programmable Memory Mask:
[MMASK_DEV12]
Device 12 Idle Timer: NONE
GPI Enable:
[GPI_EN_DEV12]
GPI Polarity Select:
[GPI_POL_DEV12]
GPI Edge Detect Enable:
[GPI_EDG_DEV12]
Device 12 ISA Forwarding Enable:
[EIO_EN_DEV12]
Global Standby Timer Reload:
[GRLD_EN_DEV12]
Burst Timer Reload (Fast Burst Only): [BRLD_EN_DEV12]
Trap SMI#:
[TRP_EN_DEV12] [TRP_STS_DEV12]
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