82371AB Datasheet, PDF (177/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
The IRR can be read when, prior to the I/O read cycle, a Read Register Command is issued with OCW3 (RR=1,
RIS=0). The ISR can be read when, prior to the I/O read cycle, a Read Register Command is issued with OCW3
(RR=1, RIS=1).
The interrupt controller retains the ISR/IRR status read selection following each write to OCW3. Therefore, there
is no need to write an OCW3 before every status read operation, as long as the current status read corresponds
to the previously selected register. For example, if the ISR is selected for status read by an OCW3 write, the ISR
can be read over and over again without writing to OCW3 again. However, to read the IRR, OCW3 will have to
be reprogrammed for this status read prior to the OCW3 read to check the IRR. This is not true when poll mode
is used. Polling Mode overrides status read when P=1, RR=1 in OCW3.
After initialization the Interrupt Controller is set to read the IRR.
As stated, OCW1 is used for reading the IMR. The output data bus will contain the IMR status whenever I/O
read is active the address is 021h or 061h (OCW1).
8.6.8. INTERRUPT STEERING
PIIX4 can be programmed to allow four PCI programmable interrupts (PIRQ[A:D]#) to be internally routed to one
of 11 interrupts IRQ[15,14,12:9,7:3]. PCLK is used to synchronize the PIRQx# inputs. The PIRQx# lines are run
through an internal multiplexer that assigns, or routes, an individual PIRQx# line to any one of 11 IRQ inputs.
The assignment is programmable through the PIRQx Route Control registers. One or more PIRQx# lines can be
routed to the same IRQx input. If interrupt steering is not required, the Route Registers can be programmed to
disable steering.
Bits [3:0] in each PIRQx Route Control register are used to route the associated PIRQx# line to an internal IRQ
input. Bit 7 in each register is used to disable routing of the associated PIRQx#.
The PIRQx# lines are defined as active low, level sensitive to allow multiple interrupts on a PCI Board to share a
single line across the connector. When a PIRQx# is routed to specified IRQ line, the software must change the
IRQ’s corresponding ELCR bit to level sensitive mode. Note, that this means that the selected IRQ can no longer
be used by an ISA device.
PRELIMINARY
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4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)