82371AB Datasheet, PDF (82/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
4.2.3.2.
TMRSTS—Timer Status Registers (IO)
I/O Address:
Default Value:
Attribute:
Counter 0—040h; Counter 1—041h; Counter 2—042h
Bits[6:0]=X; Bit 7=0
Read Only
Each counter’s status byte can be read following an Interval Timer Read Back Command. If latch status is
chosen (bit 4=0, Read Back Command) as a read back option for a given counter, the next read from the
counter’s Counter Access Ports Register returns the status byte.
Bit
Description
7 Counter OUT Pin State. 1=Pin is 1; 0=Pin is 0.
6 Count Register Status. This bit indicates when the last count written to the Count Register (CR)
has been loaded into the counting element (CE). 0=Count has been transferred from CR to CE and
is available for reading. 1=Count has not been transferred from CR to CE and is not yet available for
reading.
5:4 Read/Write Selection Status. Bits[5:4] reflect the read/write selection made through bits[5:4] of the
Control Register.
Bit[5:4]
00
01
10
11
Function
Counter Latch Command
R/W Least Significant Byte (LSB)
R/W Most Significant Byte (MSB)
R/W LSB then MSB
3:1 Mode Selection Status. Bits[3:1] return the counter mode programming.
Bit[3:1]
000
001
X10
Mode Selected
0
1
2
Bit[3:1]
X11
100
101
Mode Selected
3
4
5
0 Countdown Type Status. 0=Binary countdown; 1=Binary coded decimal (BCD) countdown.
4.2.3.3.
TMRCNT—Timer Count Registers (IO)
I/O Address:
Default Value:
Attribute:
Counter 0—040h; Counter 1—041h; Counter 2—042h
All bits undefined
Read/Write
Each of these I/O ports is used for writing count values to the Count Registers; reading the current count value
from the counter by either an I/O read, after a Counter-Latch Command, or after a Read-Back Command; and
reading the status byte following a Read Back Command.
Bit
Description
7:0 Counter Port bit[x]. Each counter I/O port address is used to program the 16-bit Count Register.
The order of programming, either LSB only, MSB only, or LSB then MSB, is defined with the Interval
Counter Control Register. The counter I/O port is also used to read the current count from the Count
Register and return counter programming status following a Read Back Command.
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