82371AB Datasheet, PDF (184/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
128 bytes of battery backed SRAM, and will be accessible even when the RTC module is disabled (via the RTC
configuration register).
All data movement between the host CPU and RTC is done through registers mapped to the ISA I/O space at
locations 70–73h.
I/O locations 70h and 71h are the standard ISA location for the RTC. The map for this bank is shown in Table 27.
Locations 72h and 73h are for accessing the extended RAM, and may be disabled.
The first 10 bytes contain information about date and time. It is up to the programmer to make sure that data
stored in these locations is within the reasonable values and represents a possible date and time. The exception
to these ranges is to store a value of C0h−FFh in the alarm bytes to indicate a “don’t care” situation. Note that bit
7 (UIP) of Control Register A should be read as 0 before each access to these locations. Bit 7 (SET) of Control
Register B should be 1 while programming these locations to avoid clashes with an update cycle.
The extended RAM bank is also accessed using an indexed scheme. ISA I/O address 72h is used as the
address pointer and ISA I/O address 73h is used as the data register. Index addresses above 127h are
not valid.
The internal RTC registers can only be accessed by PCI masters. ISA master access is not supported.
Table 27. RTC (Standard) RAM Bank
Index Address
Name
00h
Seconds
01h
Seconds Alarm
02h
Minutes
03h
Minutes Alarm
04h
Hours
05h
Hours Alarm
06h
Day of Week
07h
Date of Month
08h
Month
09h
Year
0Ah
Register A
0Bh
Register B
0Ch
Register C
0Dh
Register D
0Eh–7Fh
114 Bytes of User RAM
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