82371AB Datasheet, PDF (6/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
4.2.3.3. TMRCNT—Timer Count Registers (IO) .......................................................................................82
4.2.4. NMI Registers ......................................................................................................................................83
4.2.4.1. NMISC—NMI Status and Control Register (IO) ...........................................................................83
4.2.4.2. NMIEN—NMI Enable Register (Shared with Real-Time Clock Index Register) (IO) ...................84
4.2.5. Real Time Clock Registers ..................................................................................................................84
4.2.5.1. RTCI—Real-Time Clock Index Register (Shared with NMI Enable Register) (IO) ......................84
4.2.5.2. RTCD—Real-Time Clock Data Register (IO)...............................................................................85
4.2.5.3. RTCEI—Real-Time Clock Extended Index Register (IO).............................................................85
4.2.5.4. RTCED—Real-Time Clock Extended Data Register (IO) ............................................................85
4.2.6. Advanced Power Management (APM) Registers................................................................................86
4.2.6.1. APMC—Advanced Power Management Control Port (IO)...........................................................86
4.2.6.2. APMS—Advanced Power Management Status Port (IO) ............................................................86
4.2.7. X-Bus, Coprocessor, and Reset Registers .........................................................................................86
4.2.7.1. RIRQ—Reset X-Bus IRQ12/M and IRQ1 Register (IO)...............................................................86
4.2.7.2. P92—Port 92 Register (IO)...........................................................................................................87
4.2.7.3. CERR—Coprocessor Error Register (IO) ....................................................................................87
4.2.7.4. RC—Reset Control Register (IO) .................................................................................................88
5.0. IDE CONTROLLER REGISTER DESCRIPTIONS (PCI FUNCTION 1) ......................................................89
5.1. IDE Controller PCI Configuration Registers (PCI Function 1)....................................................................89
5.1.1. VID—Vendor Identification Register (Function 1)................................................................................89
5.1.2. DID—Device Identification Register (Function 1)................................................................................89
5.1.3. PCICMD—PCI Command Register (Function 1) ................................................................................89
5.1.4. PCISTS—PCI Device Status Register (Function 1)............................................................................90
5.1.5. RID—Revision Identification Register (Function 1) .............................................................................91
5.1.6. CLASSC—Class Code Register (Function 1) .....................................................................................91
5.1.7. MLT—Master Latency Timer Register (Function 1) ............................................................................91
5.1.8. HEDT—Header Type Register (Function 1)........................................................................................92
5.1.9. BMIBA—Bus Master Interface Base Address Register (Function 1)..................................................92
5.1.10. IDETIM—IDE Timing Register (Function 1) ......................................................................................93
5.1.11. SIDETIM—Slave IDE Timing Register (Function 1)..........................................................................95
5.1.12. UDMACTL—Ultra DMA/33 Control Register (Function 1) ................................................................96
5.1.13. UDMATIM—Ultra DMA/33 Timing Register (Function 1) ..................................................................96
5.2. IDE Controller IO Space Registers.............................................................................................................99
5.2.1. BMICX—Bus Master IDE Command Register (IO).............................................................................99
5.2.2. BMISX—Bus Master IDE Status Register (IO) .................................................................................100
5.2.3. BMIDTPX—Bus Master IDE Descriptor Table Pointer Register (IO)................................................101
6.0. USB HOST CONTROLLER REGISTER DESCRIPTIONS (PCI FUNCTION 2)........................................102
6.1. USB Host Controller PCI Configuration Registers (PCI Function 2)........................................................102
6.1.1. VID—Vendor Identification Register (Function 2)..............................................................................102
6.1.2. DID—Device Identification Register (Function 2)..............................................................................102
6.1.3. PCICMD—PCI Command Register (Function 2) ..............................................................................103
6.1.4. PCISTS—PCI Device Status Register (Function 2)..........................................................................103
6
PRELIMINARY
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)