82371AB Datasheet, PDF (193/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
Table 28. IDE Legacy I/O port definition: COMMAND BLOCK (CS1x# chip select)
IO Offset
Register Function (Read/Write)
Access
00h
Data
R/W
01h
Error/Features
R/W
02h
Sector Count
R/W
03h
Sector Number
R/W
04h
Cylinder Low
R/W
05h
Cylinder High
R/W
06h
Drive/Head
R/W
07h
Status/Command
R/W
The Data Register is accessed as a 16-bit register for PIO transfers (except for ECC bytes). All other registers
are accessed as 8-bit quantities.
Table 29. IDE Legacy I/O port definition: CONTROL BLOCK (CS3x# chip select)
IO Offset
Register Function (Read/Write)
Access
00h
Reserved
reserved
01h
Reserved
reserved
02h
Alt Status/Device control
R/W
03h
Forward to ISA (Floppy)
R/W
PIIX4 claims all accesses to these ranges, if enabled. The byte enables do not have to be externally decoded to
assert DEVSEL#. Accesses to byte 3 of the Control Block are forwarded to ISA where the floppy disk controller
responds.
Each of the two drives (drive 0 or 1) on a cable implement separate ATA register files. To determine the targeted
drive, PIIX4 shadows the value of bit 4 (drive bit) of byte 6 (drive/head register) of the ATA command block
(CS1x#) for each of the two IDE connectors (primary and secondary).
9.3. PIO IDE Transactions
The PIIX4 IDE controller includes both compatible and fast timing modes. The fast timing modes can be enabled
only for the IDE data ports. All other transactions to the IDE registers are run in single transaction mode with
compatible timings. The PIIX4 IDE signals are controlled with the granularity of the PCI clock.
Up to two IDE devices may be attached per IDE connector (drive 0 and drive 1). The IDETIM and SIDETIM
Registers permit different timing modes to be programmed for drive 0 and drive 1 of the same connector.
The Ultra DMA/33 synchronous DMA timing modes can also be applied to each drive by programming the
SDMACTL and SDMATIM registers. When a drive is enabled for synchronous DMA mode operation, the DMA
PRELIMINARY
193
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)