82371AB Datasheet, PDF (60/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
4.1.12. TOM—TOP OF MEMORY REGISTER (FUNCTION 0)
Address Offset:
Default Value:
Attribute:
69h
02h
Read/Write
This register enables the forwarding of ISA or DMA memory cycles to the PCI Bus and sets the top of
main memory accessible by ISA or DMA devices. In addition, this register controls the forwarding of ISA or DMA
accesses to the lower BIOS region (E0000–EFFFFh) and the 512–640-Kbyte main memory region (80000–
9FFFFh).
Bit
Description
7:4 Top Of Memory. The top of memory can be assigned in 1-Mbyte increments from 1–16 Mbytes. ISA
or DMA accesses within this region, and not in the memory hole region, are forwarded to PCI.
Bits[7:4] Top of Memory Bits[7:4] Top of Memory Bits[7:4] Top of Memory
0000
0001
0010
0011
0100
0101
1 Mbyte
2 Mbyte
3 Mbyte
4 Mbyte
5 Mbyte
6 Mbyte
0110
0111
1000
1001
1010
7 Mbyte
8 Mbyte
9 Mbyte
10 Mbyte
11 Mbyte
1011
1100
1101
1110
1111
12 Mbyte
13 Mbyte
14 Mbyte
15 Mbyte
16 Mbyte
Note that PIIX4 only supports a main memory hole at the top of 16 Mbytes. Thus, if a 1-Mbyte
memory hole is created for the Host-to-PCI Bridge DRAM controller between 15 and 16 Mbytes,
PIIX4 Top Of Memory should be set at 15 Mbytes.
3 ISA/DMA Lower BIOS Forwarding Enable. 1=Enable (forwarded to PCI, if XBCS Register bit 6=0);
0=Disable (contained to ISA). Note that If the XBCS Register bit 6=1, ISA/DMA accesses in this
region are always contained to ISA.
2 640–768-Kbyte Memory Region (A0000–BFFFFh) Enable. 1=Enable (ISA Master and DMA cycles
forwarded to PCI); 0=Disable (contained to ISA).
1 ISA/DMA 512–640-Kbyte Region Forwarding Enable. 1=Enable (ISA Master and DMA cycles
forwarded to PCI); 0=Disable (contained to ISA).
0 Reserved.
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INTEL CONFIDENTIAL
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