82371AB Datasheet, PDF (20/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
Name
MEMW#
REFRESH#
RSTDRV
SA[19:0]
SBHE#
SD[15:0]
SMEMR#
20
Type
Description
I/O MEMORY WRITE. MEMW# is the command to a memory slave that it may latch data
from the ISA data bus. MEMW# is an output when PIIX4 owns the ISA Bus. MEMW#
is an input when an ISA master, other than PIIX4, owns the ISA Bus. For DMA cycles,
PIIX4, as a master, asserts MEMW#.
During Reset: High-Z After Reset: High
During POS: High
I/O REFRESH. As an output, REFRESH# is used by PIIX4 to indicate when a refresh
cycle is in progress. It should be used to enable the SA[7:0] address to the row
address inputs of all banks of dynamic memory on the ISA Bus. Thus, when MEMR#
is asserted, the entire expansion bus dynamic memory is refreshed. Memory slaves
must not drive any data onto the bus during refresh. As an output, this signal is driven
directly onto the ISA Bus. This signal is an output only when PIIX4 DMA refresh
controller is a master on the bus responding to an internally generated request for
refresh.
As an input, REFRESH# is driven by 16-bit ISA Bus masters to initiate refresh cycles.
During Reset: High-Z After Reset: High
During POS: High
O RESET DRIVE. PIIX4 asserts RSTDRV to reset devices that reside on the ISA/EIO
Bus. PIIX4 asserts this signal during a hard reset and during power-up. RSTDRV is
asserted during power-up and negated after PWROK is driven active. RSTDRV is
also driven active for a minimum of 1 ms if a hard reset has been programmed in the
RC register.
During Reset: High
After Reset: Low
During POS: Low
I/O SYSTEM ADDRESS[19:0]. These bi-directional address lines define the selection
with the granularity of 1 byte within the 1-Megabyte section of memory defined by the
LA[23:17] address lines. The address lines SA[19:17] that are coincident with
LA[19:17] are defined to have the same values as LA[19:17] for all memory cycles.
For I/O accesses, only SA[15:0] are used, and SA[19:16] are undefined. SA[19:0] are
outputs when PIIX4 owns the ISA Bus. SA[19:0] are inputs when an external ISA
Master owns the ISA Bus.
During Reset: High-Z After Reset: Undefined During POS: Last SA
I/O SYSTEM BYTE HIGH ENABLE. SBHE# indicates, when asserted, that a byte is
being transferred on the upper byte (SD[15:8]) of the data bus. SBHE# is negated
during refresh cycles. SBHE# is an output when PIIX4 owns the ISA Bus. SBHE# is
an input when an external ISA master owns the ISA Bus.
During Reset: High-Z After Reset: Undefined During POS: High
I/O SYSTEM DATA. SD[15:0] provide the 16-bit data path for devices residing on the ISA
Bus. SD[15:8] correspond to the high order byte and SD[7:0] correspond to the low
order byte. SD[15:0] are undefined during refresh.
During Reset: High-Z After Reset: Undefined During POS: High-Z
O STANDARD MEMORY READ. PIIX4 asserts SMEMR# to request an ISA memory
slave to drive data onto the data lines. If the access is below the 1-Mbyte range
(00000000h–000FFFFFh) during DMA compatible, PIIX4 master, or ISA master
cycles, PIIX4 asserts SMEMR#. SMEMR# is a delayed version of MEMR#.
During Reset: High-Z After Reset: High
During POS: High
PRELIMINARY
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)