82371AB Datasheet, PDF (24/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
2.1.5. INTERRUPT CONTROLLER/APIC SIGNALS
Name
APICACK#/
GPO12
APICCS#/
GPO13
APICREQ#/
GPI5
INTR
IRQ0/
GPO14
IRQ1
Type
Description
O APIC ACKNOWLEDGE. This active low output signal is asserted by PIIX4 after its
internal buffers are flushed in response to the APICREQ# signal. When the I/O APIC
samples this signal asserted it knows that PIIX4’s buffers are flushed and that it can
proceed to send the APIC interrupt. The APICACK# output is synchronous to
PCICLK.
If the external APIC is not used, then this is a general-purpose output.
During Reset: High
After Reset: High
During POS: High/GPO
O APIC CHIP SELECT. This active low output signal is asserted when the APIC Chip
Select is enabled and a PCI originated cycle is positively decoded within the
programmed I/O APIC address space.
If the external APIC is not used, this pin is a general-purpose output.
During Reset: High
After Reset: High
During POS: High/GPO
I APIC REQUEST. This active low input signal is asserted by an external APIC
device prior to sending an interrupt over the APIC serial bus. When PIIX4 samples
this pin active it will flush its F-type DMA buffers pointing towards PCI. Once the
buffers are flushed, PIIX4 asserts APICACK# which indicates to the external APIC
that it can proceed to send the APIC interrupt. The APICREQ# input must be
synchronous to PCICLK.
If the external APIC is not used, this pin is a general-purpose input.
OD INTERRUPT. See CPU Interface Signals.
O INTERRUPT REQUEST 0. This output reflects the state of the internal IRQ0 signal
from the system timer.
If the external APIC is not used, this pin is a general-purpose output.
During Reset: Low
After Reset: Low
During POS: IRQ0/GPO
I INTERRUPT REQUEST 1. IRQ1 is always edge triggered and can not be modified
by software to level sensitive. A low to high transition on IRQ1 is latched by PIIX4.
IRQ1 must remain asserted until after the interrupt is acknowledged. If the input goes
inactive before this time, a default IRQ7 is reported in response to the interrupt
acknowledge cycle.
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4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)