82371AB Datasheet, PDF (204/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
Table 32. Clock Control Programming Modes
Clock Control Mode
Register Read
CC_EN STP_CLK_EN SLEEP_EN THT_EN
Thermal Throttle
X
X
X
X
Disable Clock Control
0
X
X
X
Stop Grant/Quick Start
LVL 2
1
X
without Throttle
X
0
Stop Grant/Quick Start
LVL 2
1
X
with Throttle
X
1
Reserved
LVL 3
1
0
0
X
Sleep
LVL 3
1
0
1
X
Stop Clock
LVL 3
1
1
0
X
Deep Sleep
LVL 3
1
1
1
X
Enable Burst Execution¹
LVL 3
1
X
X
X
NOTES:
1. Burst execution is enabled for any of the above modes (except disabled and thermal throttle) if BRST_EN bit
is set.
Stop GRANT or Quick Start State: Initiated by a read to the LVL2 register, the STPCLK# signal is asserted
and PIIX4 waits for the processor to issue a Stop Grant bus cycle. When Stop Grant cycle is terminated, PIIX4
asserts the ZZ pin to the L2 SRAM, if the [ZZ_EN] bit is set. PIIX4 does not assert the CPU_STP# signal and the
Host clocks remain running in this state. In this state, the processor disables clocks to portions of its internal
logic, but is able to snoop host bus cycles in order to maintain cache coherency. To exit this state, PIIX4 negates
the ZZ signal (if applicable) and then negates STPCLK#.
Sleep State: Initiated by a read to the LVL3 register, the STPCLK# signal is asserted and the processor issues
a Stop Grant bus cycle. When Stop Grant cycle is terminated, PIIX4 asserts the ZZ pin to the L2 SRAM if the
[ZZ_EN] bit is set and after 50 PCI clocks asserts the SLP# signal. PIIX4 does not assert the CPU_STP# signal
and the Host clocks remain running in this state. In this state, the processor disables clocks to portions of its
internal logic. The processor does not snoop host bus cycles and system designers must ensure that no host
cycles to main memory are executed by other system masters. Disabling of the PCI arbiter is a method used by
the Host Controller, for example. To exit this state, PIIX4 negates the SLP# signal, waits approximately 32 µs
and then negates the ZZ signal (if applicable); two PCI clocks later STPCLK# is negated.
Stop CLOCK State (Pentium II processor only): Initiated by a read to the LVL3 register, the STPCLK# signal
is asserted and the processor issues a Stop Grant Bus Cycle. When Stop Grant cycle is terminated, PIIX4
asserts the ZZ pin to the L2 SRAM if the [ZZ_EN] bit is set, asserts the SUS_STAT1# signal to Host Bridge to
enable Suspend Refresh for the DRAM, and then asserts the CPU_STP# signal to the clock synthesizer. The
Host clocks stop running in this state. The processor does not snoop host bus cycles and system designers
must ensure that no host cycles to main memory are executed by other system masters. To exit this state, PIIX4
negates the CPU_STP# signal. At this time PIIX4 loads the Fast Burst Timer (see below) with the [CPU_LCK]
value and count down allowing time for the processor PLL to lock. After the timer expires, PIIX4 negates the
SUS_STAT1# signal, the ZZ signal (if applicable), and finally STPCLK#.
Deep Sleep State (Pentium II processor only): Initiated by a read to the LVL3 register, the STPCLK# signal is
asserted and the processor issues a Stop Grant Bus Cycle. When Stop Grant cycle is terminated, PIIX4 asserts
the ZZ pin to the L2 SRAM if the [ZZ_EN] bit is set, asserts the SLP# signal, asserts the SUS_STAT1# signal to
Host Bridge to enable Suspend Refresh for the DRAM and then asserts the CPU_STP# signal to the clock
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