82371AB Datasheet, PDF (29/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
Name
PDCS3#
PDD[15:0]
PDDACK#
PDDREQ
Type
Description
O PRIMARY DISK CHIP SELECT FOR 3F0−3F7 RANGE. For ATA control register block.
If the IDE signals are configured for Primary and Secondary, this output signal is
connected to the corresponding signal on the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is
used for the Primary Master connector.
During Reset: High
After Reset: High
During POS: High
I/O PRIMARY DISK DATA[15:0]. These signals are used to transfer data to or from the IDE
device. If the IDE signals are configured for Primary and Secondary, these signals are
connected to the corresponding signals on the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is
used for the Primary Master connector.
During Reset: High-Z
After Reset: Undefined¹ During POS: PDD
O PRIMARY DMA ACKNOWLEDGE. This signal directly drives the IDE device DMACK#
signal. It is asserted by PIIX4 to indicate to IDE DMA slave devices that a given data
transfer cycle (assertion of PDIOR# or PDIOW#) is a DMA data transfer cycle. This
signal is used in conjunction with the PCI bus master IDE function. It is not associated
with any AT compatible DMA channel.
If the IDE signals are configured for Primary and Secondary, this signal is connected to
the corresponding signal on the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is
used for the Primary Master connector.
During Reset: High
After Reset: High
During POS: High
I PRIMARY DISK DMA REQUEST. This input signal is directly driven from the IDE
device DMARQ signal. It is asserted by the IDE device to request a data transfer, and
used in conjunction with the PCI bus master IDE function. It is not associated with any
AT compatible DMA channel.
If the IDE signals are configured for Primary and Secondary, this signal is connected to
the corresponding signal on the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is
used for the Primary Master connector.
PRELIMINARY
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4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)