82371AB Datasheet, PDF (70/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
4.2.1.3.
DR—DMA Request Register (IO)
I/O Address:
Default Value:
Attribute:
Channels 0–3—09h; Channels 4–7—0D2h
Bits[1:0]=undefined; Bits[7:2]=0 (CPURST or Master Clear)
Write Only
The Request Register is used by software to initiate a DMA request. The DMA responds to the software request
as though DREQx is asserted. These requests are non-maskable and subject to prioritization by the priority
encoder network. For a software request, the channel must be in Block Mode. The Request Register status for
DMA1 and DMA2 is output on bits [7:4] of a Status Register read.
Bit
Description
7:3 Reserved. Must be 0.
2 DMA Channel Service Request. 0=Resets the individual software DMA channel request bit. 1=Sets
the request bit. Generation of a TC also sets this bit to 0.
1:0 DMA Channel Select. Bits [1:0] select the DMA channel mode register to program with bit 2.
Bits[1:0]
00
01
10
11
Channel
Channel 0
Channel 1 (5)
Channel 2 (6)
Channel 3 (7)
4.2.1.4.
WSMB—Write Single Mask Bit (IO)
I/O Address:
Default Value:
Attribute:
Channels 0–3—0Ah; Channels 4–7—0D4h
Bits[1:0]=undefined; Bit 2=1; Bits[7:3]=0 (CPURST or a Master Clear)
Write Only
A channel’s mask bit is automatically set when the Current Byte/Word Count Register reaches terminal count
(unless the channel is programmed for autoinitialization). Setting the entire register disables all DMA requests
until a clear mask register instruction allows them to occur. This instruction format is similar to the format used
with the DMA Request Register. Masking DMA channel 4 (DMA controller 2, channel 0) also masks DMA
channels [3:0].
Bit
Description
7:3 Reserved. Must be 0.
2 Channel Mask Select. 1=Disable DREQ for the selected channel. 0=Enable DREQ for the selected
channel.
1:0 DMA Channel Select. Bits [1:0] select the DMA Channel Mode Register for bit 2.
Bits[1:0]
00
01
10
11
Channel
Channel 0 (4)
Channel 1 (5)
Channel 2 (6)
Channel 3 (7)
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