82371AB Datasheet, PDF (126/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
7.1.16. DEVACTB—DEVICE ACTIVITY B (FUNCTION 3)
Address Offset:
Default Value:
Attribute:
58–5Bh
00h
Read/Write
This register contains the Clock Event and Global Timer Reload enables for IRQs, PCI access, PME events,
Video.
Bit
Description
31:25 Reserved.
25 APMC Enable (APMC_EN)—R/W. 1=Enable generation of SMI# when APMC register is read and
SMI# is enabled. 0=Disable.
24 Video Enable (VIDEO_EN)—R/W. 1=Enable the video detect (PCI Bus utilization) logic to generate
a timer reload event for device monitor 11. 0=Disable. This logic detects PCI bus utilization as set by
the two fields: BUS_UTIL, and %BUS_UTIL.
23:16
Percentage Bus Utilization Threshold (%BUS_UTIL)—R/W. This field controls the percentage of
time that the minimum bus utilization threshold (represented by the BUS_UTIL field) must be
maintained in order to generate a video event. The actual count is measured by the number of time
slices that exceed BUS_UTIL within a 256 time slice window.
15:8 Bus Utilization Threshold (BUS_UTIL)—R/W. This field controls the threshold for bus utilization
detection. If the video detect logic finds more PCI data phases than specified by BUS_UTIL within a
256 clock period (time slice), then that time slice is counted.
7 Reserved.
6 IRQ Global Reload Enable (GRLD_EN_IRQ)—R/W. 1=Enable an unmasked IRQ[1,3:7,9:15], NMI,
or INIT to, when asserted, reload the Global Standby Timer. 0=Disable.
5 IRQ8# Clock Event Enable (BRLD_EN_IRQ8)—R/W. 1=Enable an unmasked IRQ8# to, when
asserted, generate a Fast Burst Timer reload or Stop Break event. 0=Disable.
4 PME Clock Event Enable (BRLD_EN_PME)—R/W. 1=Enable an asserted SMI#, GPI1#,
PWRBTN#, or LID signal to generate a Fast Burst Timer reload or Stop Break event. 0=Disable.
3 Undefined. Must be written as a 0.
2 Keyboard/Mouse Global Reload Enable (GRLD_EN_KBC_MS)—R/W. 1=Enable an assertion of
IRQ1 or IRQ12/M to reload the Global Standby Timer. 0=Disable.
1 IRQ Clock Event Enable (BRLD_EN_IRQ)—R/W. 1=Enable an unmasked IRQ[1,3:7,9:15], NMI, or
INIT to generate a Burst event or Stop Break event. 0=Disable.
0 IRQ0 Clock Event Enable (BRLD_EN_IRQ0)—R/W. 1=Enable an unmasked IRQ0 to generate
a Burst event or Stop Break event. 0=Disable.
126
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