82371AB Datasheet, PDF (136/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
7.1.30. SMBSHDW1—SMBUS SLAVE SHADOW PORT 1 (FUNCTION 3)
Address Offset:
Default Value:
Attribute:
D4h
00h
Read/Write
Bit
Description
7:1 SMBus Slave Address for shadow port 1 (SLVPORT1)—R/W. Specifies the address used to
match against incoming SMBus addresses for shadow port 1.
0 Read/Write for shadow port 1 (SLVPORT1RW)—R/W. This bit must be programmed to 0 since
PIIX4 SMBus slave controller only responds to Word Write transactions.
7.1.31. SMBSHDW2—SMBUS SLAVE SHADOW PORT 2 (FUNCTION 3)
Address Offset:
Default Value:
Attribute:
D5h
00h
Read/Write
Bit
Description
7:1 SMBus Slave Address for shadow port 2 (SLVPORT2)—R/W. Specifies the address used to
match against incoming SMBus addresses for shadow port 2.
0 Read/Write for shadow port 2 (SLVPORT2RW)—R/W. This bit must be programmed to 0 since
PIIX4 SMBus slave controller only responds to Word Write transactions.
7.1.32. SMBREV—SMBUS REVISION IDENTIFICATION (FUNCTION 3)
Address Offset:
Default Value:
Attribute:
D6h
00h
Read Only
Bit
Description
7:0 Revision ID (REVID)—RO. This register returns the current revision ID for the SMBus Host/Slave
controller.
136
PRELIMINARY
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)