82371AB Datasheet, PDF (160/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
Block Transfer Mode
In Block Transfer mode, the DMA is activated by DREQ to continue making transfers during the service until a
TC, caused by either a byte/word count going to FFFFh, is encountered. DREQ need only be held active until
DACK# becomes active. If the channel has been programmed for it, an autoinitialization occurs at the end of the
service. In this mode, it is possible to lock out other devices for a period of time (including refresh) if the transfer
count is programmed to a large number.
NOTE
Block mode transfers are not supported with type F DMA.
Demand Transfer Mode
In Demand Transfer mode, the DMA channel is programmed to continue making transfers until a TC (Terminal
Count) is encountered, or until the DMA I/O device releases DREQ. Thus, transfers may continue until the I/O
device has exhausted its data capacity. After the I/O device catches up, the DMA service is re-established when
the DMA I/O device reasserts the channel’s DREQ. During the time between services when the system is
allowed to operate, the intermediate values of address and byte/word count are stored in the DMA controller
Current Address and Current Byte/Word Count Registers. A TC can cause an autoinitialize at the end of the
service, if the channel has been programmed for it.
Cascade Mode
In Cascade Mode, the DMA controller will respond to DREQ with DACK, but PIIX4 will not drive IOR#, IOW#,
MEMR#, MEMW#, LA[23:17], SA[19:0], and SBHE#.
Cascade mode is also used to allow direct access of the system by 16-bit bus masters. These devices use the
DREQ and DACK signals to arbitrate for the ISA Bus. The ISA master asserts its ISA master request line
(DREQ[x]) to the DMA internal arbiter. If the ISA master wins the arbitration, PIIX4 responds with an ISA master
acknowledge (DACK[x]) signal active. Upon sampling the DACK[x] line active, the ISA master takes control of
the ISA Bus. While an ISA Master owns the bus, BALE is always driven high while AEN is always driven low.
The ISA master has control of the ISA Bus and may run cycles until it negates the DREQ[x] line.
8.4.2. DMA TRANSFER TYPES
Each of the three active transfer modes (Single, Block, or Demand) can perform three different types of
transfers. These are Read, Write and Verify.
Write Transfers
Write transfers move data from an ISA I/O device to memory located on the ISA Bus or in system DRAM. For
transfers using compatible timing, PIIX4 will activate ISA Memory control signals to indicate a memory write as
soon as the DMA provides the address. The PCI transfer is initiated after the data is valid on the ISA Bus. Data
steering is used to steer the data to the correct byte lane during these DMA transfers. When the memory is
located on the ISA Bus, a PCI cycle is not initiated.
The DMA device (I/O device) is either an 8- or 16-bit device and is located on the ISA Bus. The DMA device size
is fixed for each channel.
160
PRELIMINARY
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)