82371AB Datasheet, PDF (232/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
11.4.3. SYSTEM SUSPEND AND RESUME CONTROL SIGNALING
PIIX4 automatically controls the signals required to transition the system between the various power states. It
provides control for Host and PCI clocks, main memory and video memory refresh, system power plane control,
and system reset.
Figure 15–Figure 17 show the system timings for changing the power states of a system using the standard
POS/STR/STD models. The table notes provide information on how these signals operate in non-standard
modes of operation (e.g., Suspend to RAM mode without removing Core well power).
11.4.3.1.
Power Supply Timings
RTC Well Power
Suspend Well Power
Core Well Power
t1
t2
Figure 15. PIIX4 Power Well
Table 37. PIIX4 Power Well Timings
Sym
Parameter
Min Max Unit
t1 RTC Well Power to Suspend Well Power
0
ns
t2 Suspend Well Power to Core Well Power
0
ns
pwrseq
Notes
232
PRELIMINARY
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)