82371AB Datasheet, PDF (258/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
11.4.4. SHADOW REGISTERS
PIIX4 includes a shadow mechanism for storing the data written to the standard AT write only registers. In the
transition to Suspend mode, the contents of these registers can be read and saved so the system state can be
restored when resumed.
Once placed in the “Alternate Access” mode, various registers that would otherwise be inaccessible can be read
and written. This allows a system to restore the configuration that was present in PIIX4 before going into a
suspend state.
To enable the Alt Access mode, set the following bit to 1: PCI Function 0, Register B0h, Bit 5.
NOTE
No provisions are made for stopping events from occurring while the BIOS is reading or restoring register
values. The BIOS should exercise great care in using this feature. For example, when reading the status
of the DMA controller, all the DMA channels should be temporarily masked.
The following tables show the changes to the read and write accesses associated with the various modules.
When the Alt Access mode is enabled, some read and write cycles will cause alternative registers to be
accessed.
See the description for Miscellaneous Support Register, PCI Function 2 (offset FFh) for details on saving and
restoring the RTC Index value.
NOTE
It is assumed that no other accesses to the module will be permitted once in ALT Access Mode.
I/O Location
0000h
0000h
0001h
0001h
0002h
0002h
0003h
0003h
0004h
0004h
0005h
0005h
0006h
0006h
258
Table 51. DMA Controller Registers in Alternate Access Mode
R/W
Standard Mode Usage
ALT Access Mode
W Base Address for CH0
Current Address for CH0
R Current Address for CH0
Base Address for CH0
W Base Byte Count for CH0
Current Byte Count for CH0
R Current Byte Count for CH0
Base Byte Count for CH0
W Base Address for CH1
Current Address for CH1
R Current Address for CH1
Base Address for CH1
W Base Byte Count for CH1
Current Byte Count for CH1
R Current Byte Count for CH1
Base Byte Count for CH1
W Base Address for CH2
Current Address for CH2
R Current Address for CH2
Base Address for CH2
W Base Byte Count for CH2
Current Byte Count for CH2
R Current Byte Count for CH2
Base Byte Count for CH2
W Base Address for CH3
Current Address for CH3
R Current Address for CH3
Base Address for CH3
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4/9/97 2:23 PM PIIX4aDS
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